• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 제36회 하계학술대회 논문집 C
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• pp.1974-1976
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• 2005

The feasibility of a midgap metal gate is investigated for 32nm MOSFET low power applications. The midgap metal gate MOSFET is found to deliver a driving current as high as a bandedge gate one for the low power applications if a proper retrograde channel is used. An adequate design of the retrograde channel is essential to achieve the performance requirement given in ITRS roadmap. In addition, a process simulation is run using halo implants and thermal processes to evaluate the feasibility of the necessary retrograde profile in manufacturing environments. From the thermal budget point of view, the bandedge metal gate MOSFET is more vulnerable to the following thermal process than the midgap metal gate MOSFET since it requires a steeper retrograde doping profile. Based on the results, a guideline for the gate workfunction and the channel profile in the 32 nm MOSFET is proposed.

• Journal of Power Electronics
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• 제19권5호
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• pp.1087-1098
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• 2019

In this paper, a detuning factor (DeFac) method is proposed to design the key parameters for optimizing the transfer power and efficiency of an Inductively Coupled Power Transfer (ICPT) system with primary-secondary side compensation. Depending on the robustness of the system, the DeFac method can guarantee the stability of the transfer power and efficiency of an ICPT system within a certain range of resistive-capacitive or resistive-inductive loads. A MATLAB-Simulink model of a ICPT system was built to assess the system's main evaluation criteria, namely its maximum power ratio (PR) and efficiency, in terms of different approaches. In addition, a magnetic field simulation model was built using Ansoft to specify the leakage flux and current density. Simulation results show that both the maximum PR and efficiency of the ICPT system can reach almost 70% despite the severe detuning imposed by the DeFac method. The system also exhibited low levels of leakage flux and a high current density. Experimental results confirmed the validity and feasibility of an ICPT system using DeFac-designed parameters.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.523-526
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• 2001

In this paper, we design and fabricate the high-efficiency and low-power switched-capacitor DC-DC converter. This converter consists of internal oscillator, output driver and output switches. The internal oscillator has 100kHz oscillation frequency and the output switches composed of one pMOS transistor and three nMOS transistors. According to the configuration of two external capacitors, the converter has three functions that are the Inverter, Doubler and Divider. The proposed converter is fabricated through the 0.8$\mu\textrm{m}$ 2-poly, 2-metal CMOS process. The simulation and experimental result for fabricated IC show that the proposed converter has the voltage conversion efficiency of 98% and power efficiency more than 95%.

• Journal of Power Electronics
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• 제16권1호
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• pp.287-296
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• 2016

Conventional maximum power point tracking (MPPT) methods are ineffective under partially shaded conditions because multiple local maximum can be exhibited on power-voltage characteristic curve. This study proposes an improved cuckoo search (ICS) MPPT method after investigating the cuckoo search (CS) algorithm applied in solving multiple MPPT. The algorithm eliminates the random step in the original CS algorithm, and the conception of low-power, high-power, normal and marked zones are introduced. The adaptive step adjustment is also realized according to the different stages of the nest position. This algorithm adopts the large step in low-power and marked zones to reduce search time, and a small step in high-power zone is used to improve search accuracy. Finally, simulation and experiment results indicate that the promoted ICS algorithm can immediately and accurately track the global maximum under partially shaded conditions, and the array output efficiency can be improved.

• International Journal of Fluid Machinery and Systems
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• 제2권4호
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• pp.334-345
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• 2009

Pumped storage power plants are playing a significant role in the contribution to the stabilization of an electrical grid, above all by stable operation and fast reaction to sudden load respectively frequency changes. Optimized efficiency and smooth running characteristics both in pump and turbine operation, improved stability for synchronization in turbine mode, load control in pump mode operation and also short reaction times may be achieved using adjustable speed power units. Such variable speed power plants are applicable for high variations of head (e.g. important for low head pump-turbine projects). Due to the rapid development of power semiconductors and frequency converter technology, feasible solutions can be provided even for large hydro power units. Suitable control strategies as well as clear design criteria contribute significantly to the optimal usage of the pump turbine and motor-generators. The SIMSEN tool for dynamic simulations has been used for comparative investigations of different configurations regarding the power converter topology, types of semiconductors and types of motor-generators including the coupling to the hydraulic system. A brief overview of the advantages & disadvantages of the different solutions can also be found in this paper. Using this approach, a customized solution minimizing cost and exploiting the maximum usage of the pump-turbine unit can be developed in the planning stage of new and modernization pump storage projects.

• 한국정보통신학회논문지
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• 제6권3호
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• pp.421-426
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• 2002

Hybrid cascade multilevel PWM inverter has advantages of hybrid structure which enhances the better utilization of power semiconductor switches, that is, both hi호 power-low frequency switch, GTO and low power-high frequency switch, IGBT can be used in the same circuit. In this paper, a static var compensator using hybrid cascade 5-level PWM inverter is presented for high voltage/high power applications. The proposed system is modelled by circuit DQ transformation, and thus an equivalent circuit is obtained which reveals the important characteristics of the system and lead to the related equations. Finally, circuit structure and characteristics is presented and the validity of the characteristics analysis is shown through PSIM simulation.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 제37회 하계학술대회 논문집 C
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• pp.1601-1602
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• 2006

A cascode low noise amplifier(LNA) for a 2.45GHz RFID reader is designed using 0.25um CMOS technology. There are four LNA design techniques applied to the cascode topology. In this paper, power-constrained simultaneous noise and input matching(PCSNIM) technique is used for low power consumption and achieving the noise matching and input matching simultaneously. Simulation results demonstrate a noise figure of 2.75dB, a power gain of 10.17dB, and a dissipation power of 8.65mW with 1V supply.

• 전기학회논문지
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• 제68권1호
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• pp.98-101
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• 2019

In this paper, we propose the power-based pipelined-forwarding MAC protocol which can select relay nodes according to the residual power and energy harvesting rate in EH-WSN (energy-harvesting wireless sensor networks). The proposed MAC follows a pipelined-forwarding scheme in which nodes repeatedly sleep and wake up in an EH-WSN environment and data is continuously transmitted from a high-level node to a low-level node. The sleep interval is adaptively controlled so that nodes with low energy harvesting rate can be charged sufficiently, thereby minimizing the transmission delay and increasing the network lifetime. Simulation shows that the proposed MAC protocol improves the balance of residual power and network lifetime.

• 전력전자학회:학술대회논문집
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• 전력전자학회 1998년도 전력전자학술대회 논문집
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• pp.460-465
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• 1998

Due to high power ratings and low conduction loss, the IGBT has become more attractive in switching power supplies. However, its turn-on and turn-off characteristics cause severe switching loss and switching frequency limitation. This paper proposes 2.4kW, 48V, high efficiency half-bridge DC-DC converter using paralleled IGBT-MOSFET switch concept, where each of IGBT and MOSFET plays its part during on-periods and switching instants. The switching loss is analyzed by using the linearized model and the opteration of the converter are investigated by simulation results.

• 한국전자통신학회논문지
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• 제7권6호
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• pp.1301-1308
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• 2012

본 논문에서는 ADCL(adiabatic dynamic CMOS logic) buffer를 이용한 단열 논리회로용 AC 전원과 동기화된 저전력 클럭 발생기를 제안한다. CMOS 논리회로의 전력 손실을 줄이고 ADCL의 저전력 동작을 위해서, 논리회로의 clock 신호는 AC 전원 신호와 동기화 되어야 한다. 설계된 Schmitt trigger 회로와 ADCL buffer를 사용한 ADCL 주파수 분주기를 이용하여 AC 신호와 단열동작을 위한 clock 신호가 발생된다. 제안된 저전력 클럭 발생기의 소비전력은 3kHz와 10MHz에서 각각 1.181uW와 37.42uW으로 시뮬레이션에서 확인하였다.