• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.39 no.1
• /
• pp.66-75
• /
• 2002

For the theoretical performance analysis of Viterbi Decoder for wireless LAN with data rate 12Mbps, code rate 1/2 and constraint length 7 defined in IEEE 802.11a, the transfer function is derived using Cramer's rule and the first-event error probability and bit error probability is derived under the AWGN. In the design process, input symbol is quantized into 16 steps for 4 bit soft decision and register exchange method instead of memory method is proposed for trace back, which enables the majority at the final decision stage. In the implementation, the Viterbi decoder based on parallel architecture with pipelined scheme for processing 12Mbps high speed data rate and AWGN generator are implemented using FPGA chips. And then its performance is verified in real time.

• Journal of the Korean Crystal Growth and Crystal Technology
• /
• v.16 no.5
• /
• pp.181-188
• /
• 2006

Rutile single crystals grown by skull melting method were cut parallel and perpendicular to growth axis, and both sides of the cut wafers (${\phi}5.5mmx1.0mm$) were then polished to be mirror surfaces. The black wafers were changed into pale yellow color by annealing in air at 1200 and $1300^{\circ}C$ for $3{\sim}15\;and\;10{\sim}50$ hours, respectively. After annealing, structural and optical properties were examined by specific gravity (S.G), SEM-electron backscattered pattern (SEM-EBSP), X-ray diffraction (XRD), FT-IR transmittance spectra, laser Raman spectroscopy (LRS), photoluminescence (PL) and X-ray photoelectron spectroscopy (XPS). These results are analyzed increase of weight in air, decrease of weight in water and specific gravity, shown secondary phase of needle shape, diffusion of oxygen ion and increase of $Ti^{3+}$. From the above results, we suggest that the skull melting method grown rutile single crystals contain defect centers such as $O_v,\;Ti^{3+},\;O_v-Ti^{3+}$ interstitials and $F^+-H^+$.

• Journal of IKEEE
• /
• v.22 no.2
• /
• pp.233-241
• /
• 2018

This paper describes a lightweight implementation of a cryptographic processor supporting GCM (Galois/Counter Mode) authenticated encryption (AE) that is based on the two block cipher algorithms of ARIA and AES. It also provides five modes of operation (ECB, CBC, OFB, CFB, CTR) for confidentiality as well as the key lengths of 128-bit and 256-bit. The ARIA and AES are integrated into a single hardware structure, which is based on their algorithm characteristics, and a $128{\times}12-b$ partially parallel GF (Galois field) multiplier is adopted to efficiently perform concurrent processing of CTR encryption and GHASH operation to achieve overall performance optimization. The hardware operation of the ARIA/AES-GCM AE processor was verified by FPGA implementation, and it occupied 60,800 gate equivalents (GEs) with a 180 nm CMOS cell library. The estimated throughput with the maximum clock frequency of 95 MHz are 1,105 Mbps and 810 Mbps in AES mode, 935 Mbps and 715 Mbps in ARIA mode, and 138~184 Mbps in GCM AE mode according to the key length.

• Preventive Nutrition and Food Science
• /
• v.16 no.1
• /
• pp.18-23
• /
• 2011

Alzheimer's disease (AD) is a neurodegenerative disorder characterized by neuronal loss and extracellular senile plaques containing $\beta$-amyloid peptide (A$\beta$). The deposition of the A$\beta$ peptide following proteolytic processing of amyloid precursor protein (APP) by $\beta$-secretase (BACE1) and $\gamma$-secretase is a critical feature in the progression of AD. Among the plant extracts tested, the ethanol extract of Petasites japonicus leaves showed novel protective effect on B103 neuroblastoma cells against neurotoxicity induced by A$\beta$, as well as a strong suppressive effect on BACE1 activity. Ethanol extracts of P. japonicus leaves were sequentially extracted with methylene chloride, ethyl acetate and butanol and evaluated for potential to inhibit BACE1, as well as to suppress A$\beta$-induced neurotoxicity. Exposure to A$\beta$ significantly reduced cell viability and increased apoptotic cell death. However, pretreatment with ethyl acetate fraction of P. japonicus leaves prior to A$\beta$ (50 ${\mu}M$) significantly increased cell viability (p<0.01). In parallel, cell apoptosis triggered by A$\beta$ was also dramatically inhibited by ethyl acetate fraction of P. japonicus leaves. Moreover, the ethyl acetate fraction suppressed caspase-3 activity to the basal level at 30 ppm. Taken together, these results demonstrated that P. japonicus leaves appear to be a useful source for the inhibition and/or prevention of AD by suppression of BACE1 activity and attenuation of A$\beta$ induced neurocytotoxicity.

• The KIPS Transactions:PartB
• /
• v.12B no.5 s.101
• /
• pp.561-566
• /
• 2005

This paper presents a visual tracking algorithm for the golf swing motion analysis by using the information of the pixels of video frames and movement of the golf club to solve the problem fixed center point in model based tracking method. The model based tracking method use the polynomial function for trajectory displaying of upswing and downswing. Therefore it is under the hypothesis of the no movement of the center of gravity so this method is not for the amateurs. we proposed method using the information of pixel and movement, we first detected the motion by using the information of pixel in the frames in golf swing motion. Then we extracted the club head and hand by a properties of club shaft that consist of the parallel line and the moved location of club in up-swing and down-swing. In addition, we can extract the center point of user by tracking center point of the line between center of head and both foots. And we made an experiment with data that movement of center point is big. Finally, we can track the real trajectory of club head, hand and center point by using proposed tracking algorithm.

• Journal of Astronomy and Space Sciences
• /
• v.19 no.3
• /
• pp.215-224
• /
• 2002

This paper describes EGSE design for the small satellite such like KOMPSAT-2 satellite. Recent design trend of small satellite and EGSE is to take short development time and less cost. For this purpose, the design for KOMPSAT-2 satellite and EGSE are not much modified from KOMPSAT-1 heritage. It means that it is able to be accommodated the verified hardware and software modules used in KOMPSAT-1 satellite program if possible. The objective of EGSE is to provide hardware and software for efficient electrical testing of integrated KOMPSAT-2 satellite in three general categories. (1) Simulators for ground testing (e.g. solar-simulation power, earth scenes, horizons and sun sensor). (2) Ground station type satellite data acquisition and processing test sets. (3) Overall control of satellite using hardline datum. In KOMPSAT (KOrea Multi-Purpose SATellite) program, KOMPSAT-2 EGSE was developed to support satellite integration and test activities. The KOMPSAT-2 EGSE was designed in parallel with satellite design. Consequently, the KOMPSAT-2 EGSE was based on the KOMPSAT-1 heritage since the spacecraft design followed the heritage. The KOMPSAT-2 baseline was elaborated by taking advantage of experience from KOMPSAT-1 program. The EGSE of KOMPSAT-2 design concept is generic modular design with preference in part selection with commercial off-the-shelf which were proven from KOMPSAT-1 programs, flexible/user friendly operational environment (graphical interface preferred), minimized new design and self test capability.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.26 no.11C
• /
• pp.148-156
• /
• 2001

This paper proposed embedded application-specific microprocessor(YS-RDSP) whose structure has an additional DSP processor on chip. The YS-RDSP can execute maximum four instructions in parallel. To make program size shorter, 16-bit and 32-bit instruction lengths are supported in YS-RDSP. The YS-RDSP provides programmability. controllability, DSP processing ability, and includes eight-kilobyte on-chip ROM and eight-kilobyte RAM. System controller on the chip gives three power-down modes for low-power operation, and SLEEP instruction changes operation statue of CPU core and peripherals. YS-RDSP processor was implemented with Verilog HDL on top-down methodology, and it was improved and verified by cycle-based simulator written in C-language. The verified model was synthesized with 0.7um, 3.3V CMOS standard cell library, and the layout size was 10.7mm78.4mm which was implemented by using automatic P&R software.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.35C no.9
• /
• pp.11-20
• /
• 1998

High-speed complex-number arithmetic units are essential to baseband signal processing of modern digital communication systems such as channel equalization, timing recovery, modulation and demodulation. In this paper, a new complex-number multiplication algorithm is proposed, which is based on redundant binary (RB) arithmetic combined with radix-4 Booth recoding scheme. The proposed algorithm reduces the number of partial product by one-half as compared with the conventional direct method using real-number multipliers and adders. It also leads to a highly parallel architecture and simplified circuit, resulting in high-speed operation and low power dissipation. To demonstrate the proposed algorithm, a prototype complex-number multiplier-accumulator (CMAC) core with 10-bit operands has been designed using 0.8-$\mu\textrm{m}$ N-Well CMOS technology. The designed CMAC core contains about 18,000 transistors on the area of about 1.60 ${\times}$ 1.93 $\textrm{mm}^2$. The functional and speed test results show that it can operate with 120-MHz clock at V$\sub$DD/=3.3-V, and its power consumption is given to about 63-mW.

• Journal of Information Technology and Architecture
• /
• v.10 no.1
• /
• pp.23-31
• /
• 2013

A rapid growth of IT convergence into different application areas draws a lot of interest in high performance platform and embedded system. Industry needs well educated computer professionals with the practical understanding on the emerging technologies and core issues of contemporary popular services. In this paper, we present an education framework for computer system architecture based on rigorous analyses of the characteristics of IT convergence services and information technology trends. The proposed framework puts emphasis on real-world and hands-on subjects related to multicore architecture, embedded system and parallel processing. We believe effective use in the development and management of computer system architecture courses encouraging both industries and students.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2017.05a
• /
• pp.335-338
• /
• 2017

Currently Artificial Inteligence and Deep Learning are social issues, and These technologies are applied to various fields. A good method among the various algorithms in Artificial Inteligence is Convolutional Neural Network. Convolutional Neural Network is a form that adds convolution layers that extracts features by convolution operation on a general neural network method. If you use Convolutional Neural Network as small amount of data, or if the structure of layers is not complicated, you don't have to pay attention to speed. But the learning time is long as the size of the learning data is large and the structure of layers is complicated. So, GPU-based parallel processing is a lot. In this paper, we developed Convolutional Neural Network using CUDA and Learning speed is faster and more efficient than the method using the CPU.