• Journal of the Korean Ceramic Society
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• v.49 no.4
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• pp.347-351
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• 2012

Vermiculite-silica composites with a layered structure were fabricated by adding cellulose fibers as a pore former and by a simple uniaxial pressing and subsequent sintering process. Three different combinations of additives were used and their effects on the compressive strength and thermal conductivity of the composites were investigated. Both compressive strengths (42-128 MPa) and thermal conductivities (0.75-1.48 $W/m{\cdot}K$) in the direction perpendicular to the pressing direction (T) were higher than those (19-81 MPa and 0.32-1.04 $W/m{\cdot}K$) in the direction parallel to the pressing direction (S) in all samples. The anisotropy in both properties was attributed to the microstructural anisotropy, which was caused by the layered structure developed in the composites.

• Industrial Engineering and Management Systems
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• v.8 no.3
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• pp.155-161
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• 2009

We focus on discrete event systems with a structure of parallel processing, synchronization, and no-concurrency. We use max-plus algebra, which is an effective approach for controller design for this type of system, for modeling and formulation. Since a typical feature of this type of system is that the initial schedule is frequently changed due to unpredictable disturbances, we use a simple model and numerical examples to examine the possibility of applying the concepts of the feeding buffer and the project buffer of critical chain project management (CCPM) on max-plus linear discrete event systems in order to control the occurrence of an undesirable state change. The application of a CCPM-based framework on a max-plus linear discrete event system was proven to be effective.

• 제어로봇시스템학회:학술대회논문집
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• 1993.10a
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• pp.1052-1057
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• 1993

A scara type Direct Drive Arm(DDA) with two degrees-of-freedom is designed and implemented. The direct drive motor is used to furnish large torque to reduce the modeling error by the gear and chains. To control the DDA, a multiprocessor control structure with multirate dynamic control algorithm is designed. In the control algorithm, the dynamics of system is used to calculate the nominal control torque and the feedback controls are calculated with a parallel processing algorithm for each joint. The laboratory experiments on Hong-Ik DDA by dynamic control algorithm are presented and compared to that of PID control algorithm. This result shows that the proposed controller guarantees small trajectory error and stability. With this research, Hong-Ik DDA is expected to be utilized as A basic tool for robotics and control engineering.

• Journal of the Korea Institute of Military Science and Technology
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• v.7 no.3 s.18
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• pp.149-156
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• 2004

In this study, vibration and aeroelastic analyses of a T-tail have been conducted. The structural dynamic computations of the T-tail are performed using MSC/NASTRAN and CFD-based computational aeroelastic analysis method is used to investigate the complex flutter phenomena. The results for vibration and aeroelastic analyses in the frequency and time domains are presented. It is importantly shown that the modal coupling of the torsional mode of vertical-wing and the asymmetric bending mode of horizontal-wing parts can give sensitive effects for the flutter stability of T-tail configurations.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 1997.11a
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• pp.63-67
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• 1997

The ISO(International Standard Organization) has standardized MPEG-2 audio. The MPEG-2 audio compression algorithm is based upon subband analysis and exploits the human auditory characteristics to achieve a low bit rate with minimum perceptual loss of audio signal quality. This thesis presents an enhanced MPEG-2 audio encoder using multiple TMS320C30 general purpose DSP's. The developed system is made up of five slave boards and one master board. Each slave board performs susband analysis psychoacoustic parameter calculation for one channel, and the master board manages bit allocation, quantization, and bit-stream formatting for all channels. Parallel processing and pipelining techniques are used in hardware structure and fast algorithms are applied in each subroutine to implement a real-time process. The implemented system supports multichannel up to 5.1 and various bitrates.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.263-264
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• 2006

In this paper, an efficient and fast algorithm to reduce calculation amount of FIR(Finite Impulse Responses) filtering is proposed. Proposed algorithm enables arbitrary size of parallel processing, and their structures are also easily derived. Furthermore, it is shown that the number of multiplication/sample is reduced, and number of instructions using MAC(Multiplication and Accumulation) processor are also reduced. For theoretical improvement, numbers of sub filters are compared with those of conventional algorithm. In addition to the theoretical improvement, it is shown that number of element for hardwired implementation are reduced comparison to those of the conventional algorithm.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.29B no.10
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• pp.10-18
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• 1992

This paper considers and implementation of the memory system which provides simultaneous access to pq image points of block(p$\times$q), horizontal vector(1$\times$pq)and/vertical vector(pq$\times$1) in 2-dimension image array, where p and q are design parameters. This memory system consists of an address calculation circuit, address routing circuit, data routing circuit, module selection circuit and m memory modules where m>qp. The address calculation circuit computes pq addresses in parallel by using the difference of addresses among image points. Extra module assignment circuit is not used by improving module selection circuit with routhing circuit. By using Verilog-XL logic simulator, we verify the correctness of the memory system and estimate the performance. The implemented system provides simultaneous access to 16 image points and is 6 times faster than conventional memory system.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.8
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• pp.62-71
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• 1994

A novel semiconductor device is proposed to be used as a processing element for the implementation of pulse-mode neural networks which consists of alternating n' GaAs quantum wells and undoped AlGaAs barriers sandwitched between n' GaAs cathode and P' GaAs anode and in simple circuit in conjunction with a parallel capacitive and resistive load the trigger circuit generates neuron-like pulse train output mimicking the function of axon hillock of biological neuron. It showed the sigmoidal relationship between the frequency of the pulse-train and the applied input DC voltage. In conjunction with MQWIMD the various neural circuits are proposed especially a neural chip monolithically integrated with photodetectors in order to perfrom the pattern recognition.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.12
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• pp.9-19
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• 1997

This paper describes the design and FPGA implementation of a system control unit within a multiprocessor chip which can be used as a node processor ina massively parallel processing (MPP) caches, memory management units, a bus unit and a system control unit. Major functions of the system control unit are locking/unlocking of the shared variables of protected access, synchronization of instruction execution among four integer untis, control of interrupts, generation control of processor's status, etc. The system control unit was modeled in very high level using verilog HDL. Then, it was simulated and verified in an environment where trap handler and external interrupt controller were added. Functional blocks of the system control unit were changed into RTL(register transfer level) model and synthesized using xilinx FPGA cell library in synopsys tool. The synthesized system control unit was implemented by Xilinx FPGA chip (XC4025EPG299) after timing verification.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.6
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• pp.902-907
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• 1986

A real-time microprogrammable digital signal processor is designed and implemented using the bit-slice logic, a parallel multiplier, 74 series TTLs and MOS memories. A microinstruction set for the processor is defined and an application program development system is constructed. For its performance evalution, a digital filter and FFT are implemented with this digital signal processor. It is proved that this processor is faster than commrcially available single chip digital signal processors such as \ulcornerD 7720, AMI 2811, enabling very high speed digital signal processing.