• Journal of Biomedical Engineering Research
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• v.12 no.2
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• pp.113-120
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• 1991

This paper describes the implementation of a 3 channel ECG monitoring system. This system consists of an IBM-PC and simple accessory only. A PDTS (parallel data transmission system ) was designed to do monitor the data being operated with no effect and no exchange of software and hardware on the main transmission system in LOCAL mode. And it receives patient's ECG data from EPTS ( ECG processing and transmission system) of distant region. It provides on-line ECG waveform display, waveform storage, recall and editing the waveform. We have implemented the monitoring system by tw methods, and with system, we could directly monitor the EPTS and also receive the data from the remote ㅁe잉ion. This system was tested by experiments and examined its practical use.

• Proceedings of the Korea Multimedia Society Conference
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• 2000.04a
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• pp.117-120
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• 2000

This paper describe VLSL design of crytographic processor which can execute triple DES and DES encryption algorithm. To satisfy flexible architecture and area-efficient structure, the processor has 1 unrolled loop structure without pipeline and can support four standard mode, such as ECB, CBC, CFB, and OFB modes. To reduce overhead of key computation , the key precomputation technique is used. Also to eliminate increase of processing time due to data input and output time, background I/O techniques is used which data input and output operation execute in parallel with encryption operation of cryptographic processor. The cryptographic processor is implemented using Altera EPF10K40RC208-4 devices and has peak performance of about 75 Mbps under 20 Mhz ECB DES mode and 25 Mbps uder 20 Mhz triple DES mode.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.3
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• pp.66-76
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• 1995

In this research, a mesh connected VLSI structure is proposed for the real time computation of the generalized Hough transform(GHT). The purpose of the research is to design a generalized Hough transformer that can be realized as a single chip processor. The GHT has been modified to yield a highly parallel structure consisting of simple processing elements(PEs) and communication networks. In the proposed structure, the GHT can be computed by first assigning an image pixel to a PE and performing shift and add operations. The result of the CAD circuit simulation shows that it can be computed in the time proportional to the number of pixels in the pattern. In addition to the Hough transformer, the peak detector has been designed to reduce 1)the number of the I/O operations between the transformer and the host computer and 2) the host computer's burden for peak detection by transmitting only the local peaks detected from the transformed accumulator. It is expected that the proposed single chip Hough transformer with peak detector makes a fast and inexpensive edge based object recognition systems possible for many industrial and military applications.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.204-207
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• 2007

Film bulk acoustic wave resonator (FBAR) technology has attracted a great attention as a promising technology to fabricate the next-generation RF filters mainly because the FBAR technology can be integrated with current Si processing. The RF filters are basically composed of several FBAR devices connected in parallel and in series, and their characteristics depend highly on the FBAR device characteristics. Thus, it is important to design high quality FBAR devices by device or process optimization. This kind of effort may enhance the FBAR device characteristics, eventually leading to FBAR filters of high performance. In this paper, we describe the methods to more effectively improve the resonance characteristics of the FBAR devices.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.10
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• pp.50-62
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• 1996

A parallel looking stereo camera was mainly used as an input sensor for digital image processing, image understanding and the extraction of 3 dimensional information. Theoretical analysis and performance evaluation are dealt in this paper for a convergent looking stereo camera model having a fixation point with the result of crossing optical axes. The quantization error, depth resolution and equidepth map due to digital pixels, and the misalignments effects of pan, tilt and roll angles are analyzed by using rhe relationship between the reference and image coordinate systems. Also horopter, epipolar lines, probability density functions of the depth error, and stereo fusion areas for the two camera models are discussed.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.34S no.3
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• pp.12-23
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• 1997

In this paper, we propose a new cell switch fabric for increasing the performance of ATM switching systems. Proposed switching network consists of a sorting network and a routing network. Both of these are multistage networks where each stage performs a fixed permutation on the incoming lines, and then routes them through a clumn of 2x2 switching elements. It is designed for distributing inputs and parallel processing to reduce the hardware complexity and obtain high performance of switching network. The structure and the operation of th eswitching network aredescribed and the performanceof the switching network is anlyzed under uniform traffic models. In this result, though the size of proposed network is increased the large scale, it has always the same throughput as the that of genral output queueing system with N=2. So, it is found that our proposed network is appropriate for the high apeed and lrger size of ATM switching systems.

• Proceedings of the KIEE Conference
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• 1993.07a
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• pp.453-455
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• 1993

In this research, the digital signal processing PC board which employs TI's TMS320C25 is implemented. The board can perform following functions. spectrum analysis of speech and repetitive signal, digital filters emulation by convolution, signal generation of sinusoidal wave, rectangular wave etc.. In this system, communications between PC and DSP board. program down-loading to DSP board and recording and graphic of acquired and processed data in DSP board are executed by PC. Parallel interface and buffer memory are used in communications. Data acquisition and operation are carried out in DSP board. Resultant data are transmitted to PC and output through DAC.

• ETRI Journal
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• v.45 no.6
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• pp.1035-1045
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• 2023

We propose a novel graphics processing unit (GPU) algorithm that can handle a large-scale 3D fast Fourier transform (i.e., 3D-FFT) problem whose data size is larger than the GPU's memory. A 1D FFT-based 3D-FFT computational approach is used to solve the limited device memory issue. Moreover, to reduce the communication overhead between the CPU and GPU, we propose a 3D data-transposition method that converts the target 1D vector into a contiguous memory layout and improves data transfer efficiency. The transposed data are communicated between the host and device memories efficiently through the pinned buffer and multiple streams. We apply our method to various large-scale benchmarks and compare its performance with the state-of-the-art multicore CPU FFT library (i.e., fastest Fourier transform in the West [FFTW]) and a prior GPU-based 3D-FFT algorithm. Our method achieves a higher performance (up to 2.89 times) than FFTW; it yields more performance gaps as the data size increases. The performance of the prior GPU algorithm decreases considerably in massive-scale problems, whereas our method's performance is stable.

• ETRI Journal
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• v.46 no.5
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• pp.839-850
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• 2024

As computing systems become increasingly larger, high-performance computing (HPC) is gaining importance. In particular, as hyperscale artificial intelligence (AI) applications, such as large language models emerge, HPC has become important even in the field of AI. Important operations in hyperscale AI and HPC are mainly linear algebraic operations based on tensors. An AB21 supercomputing AI processor has been proposed to accelerate such applications. This study proposes a XEM accelerator to accelerate linear algebraic operations in an AB21 processor effectively. The XEM accelerator has outer product-based parallel floating-point units that can efficiently process tensor operations. We provide hardware details of the XEM architecture and introduce new instructions for controlling the XEM accelerator. Additionally, hardware characteristic analyses based on chip fabrication and simulator-based functional verification are conducted. In the future, the performance and functionalities of the XEM accelerator will be verified using an AB21 processor.

• Journal of Power Electronics
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• v.6 no.4
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• pp.330-339
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• 2006

This paper deals with novel electronic ballast based on single-stage power processing topology using a symmetrical half-bridge inverter and current injection circuit. The half-bridge inverter drives the output parallel resonant circuit and injects current through the power factor correction (PFC) circuit. Because of high frequency current injection and high frequency modulated voltage, the proposed circuit maintains the unity power factor (UPF) with low THD even under wide variation in ac input voltage. This circuit needs minimum and lower sized components to achieve the UPF and high efficiency. This leads to an increase in reliability of ballast at low cost. Furthermore, to reduce cost, the electronic ballast is designed for two series-connected fluorescent lamps (FL). The analysis and experimental results are presented for ($2{\times}36$ Watt) fluorescent lamps operating at 50 kHz switching frequency and input line voltage (230 V, 50 Hz).