• Proceedings of the IEEK Conference
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• 2001.06e
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• pp.169-172
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• 2001

In this paper, it used a different pipeline method from conventional method which is encoding the video signal of analog with digital. It designed with pipeline structure of 4 phases as the pixel clock ratio of the whole operation of the encoder, and secured the stable operational timing of the each sub-blocks, it was visible the effect which reduces a gate possibility as designing by the ROM table or the shift and adder method which is not used a multiplication flag method of case existing of multiplication of the fixed coefficient. The designed encoder shared with the each sub-block and it designed the FPGA using MAX+PLUS2 with VHDL.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2004.05a
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• pp.63-68
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• 2004

Since rotor position information is necessary to drive the SRM, absolute-encoder, resolver and incremental-encoder is used to detect a poor position. But, it is not desirable to use a high priced encoder and high efficient microprocessor under the condition of the simple driving system when precision control is not demanded. In this paper, Only using the reflective type 2 photosensors replace the conventional opto interrupter and slotted disk, which not only remove a slotted disk section but drive 3-phase 6/4 SRM bidirectionally. Moreover, as control circuit only is composed of common analog device economy is maximized.

• ETRI Journal
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• v.31 no.5
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• pp.585-592
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• 2009

This paper presents a method for decoding high minimal distance ($d_{min}$) short codes, termed Cortex codes. These codes are systematic block codes of rate 1/2 and can have higher$d_{min}$ than turbo codes. Despite this characteristic, these codes have been impossible to decode with good performance because, to reach high $d_{min}$, several encoding stages are connected through interleavers. This generates a large number of hidden variables and increases the complexity of the scheduling and initialization. However, the structure of the encoder is well suited for analog decoding. A proof-of-concept Cortex decoder for the (8, 4, 4) Hamming code is implemented in subthreshold 0.25-${\mu}m$ CMOS. It outperforms an equivalent LDPC-like decoder by 1 dB at BER=$10^{-5}$ and is 44 percent smaller and consumes 28 percent less energy per decoded bit.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.11C
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• pp.1083-1090
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• 2005

This paper presents the design of a video encoder for the device of need TV-OUT function. The designed video encoder satisfies the standard conditions of International Telecommunication Union-Radiocommunication (ITU-R) BT.470. ITU-R BT.470 can be classified as NTSC, PAL or SECAM. NTSC and PAL use Amplitude Modulation (AM) to transmit color difference signals and SECAM uses Frequency Modulation (FM). SECAM must have an antic-cloche filter but the filter recommended by ITU-R BT.470 is not easy to design due to sharpness of the frequency response. So formerly the filter was designed as analog. This paper proposes that the filter is designed as digital and the special quality of the filter is transformed easy to design. And the modulation method is modified to be identical with the result required at standard. The encoder can control power consumption by output mode to apply mobile phone, mobile devices, etc. The proposed encoder is experimentally demonstrated with ALTERA FPGA APEX20KE EP20K1000EBC652-3 device and SAMSUNG LCD-TV.

• The KIPS Transactions:PartB
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• v.9B no.6
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• pp.715-726
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• 2002

In this paper, we construct real-time moving picture encoder based on fractal theory by using general purpose digital signal processors. The constructed encoder is implemented using two fixed-point general DSPs (ADSP2181) and performs image encoding by three stage pipeline structure. In the first pipeline stage, the image grabber acquires image data from NTSC standard image signals and stores digital image into frame memory. In the second stage, the main controller encode image dada using fractal algorithm. The last stage, output controller perform Huffman coding and result the coded data via RS422 port. The performance tests of the constructed encoder shows over 10 frames/sec encoding speed for QCIF data when all the frames are encoded. When we encode the images using the interframe and redundency based on the proposed algorithms, encoding speed increased over 30 frames/sec in average.

• Journal of the Institute of Convergence Signal Processing
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• v.14 no.4
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• pp.249-254
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• 2013

A fast multiplier and ADC are essential to process the analog signals in real time. The double-base number system(DBNS) is known as an efficient method for this purpose. The DBNS uses the numbers 2 and 3 as the base numbers simultaneously. The system has an advantage of fast multiplication, less chip area, and low power consumption compared to the binary multiplier. However, the inherent errors of the log number's intrinsic tolerance in DBNS are accumulated in a FIR digital filter, so the signal-to-noise ratio(SNR) has a tendency to be degraded. In this paper, the nonlinear encoder of ADC is designed to compensate the accumulated errors of DBNS by analysing the error distributions of various filter coefficients. The new ADC does not sacrifice its own advantages because the encoder circuits are modified only. The experiments were done with an FIR filters those were designed to have -70dB of SNR in stop band. The proposed nonlinear ADC encoder could drop the SNR to -45dB in stop band, in contrast to -35dB with the linear encoder.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.9A
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• pp.920-927
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• 2006

There are three critical considerations in developing a PCM telemetry encoder to be installed in an artillery projectile. The first is the performance consideration, such as sampling rate and data transmission rate. The second is the size consideration due to the severely limited installation space in an artillery projectile and the last is the power consumption consideration due to limitations of the munition's power supply. To meet these three considerations, the best alternative is a one-chip solution. Using a commercially available TMS320F2812 DSP, we have implemented a 30-channel PCM telemetry encoder to process randomized data frames, composed of 16-channel analog data, 14-channel digital data and 2-frame synchronization channels per data frame at 10Mbps transmitting baud rate.

• ETRI Journal
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• v.34 no.2
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• pp.256-259
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• 2012

The double-base number system has been used in digital signal processing systems for over a decade because of its fast inner product operation and low hardware complexity. This letter proposes an innovative multiplier architecture using hybrid operands. The multiplier can easily be linked to flash analog-to-digital converters or digital systems through a double-base number encoder (DBNE) for realtime signal processing. The design of the DBNE and the multiplier enable faster digital signal processing and require less hardware resources compared to the binary processing method.

• Proceedings of the KIEE Conference
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• 1995.07b
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• pp.977-979
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• 1995

MPEG-II is the international standard of compression for digital image and digital audio that is the most important in the multimedia environment. Now many researchers are developing relevant systems. MPEG-II consists of video, audio, system and the other part. In this paper, we have designed and demonstrated two channel audio encoder system that processes the audio compression part, and excutes layer II for complexity and psychoacoustic model II, with ADSP-21020 of Analog Device.

• The Journal of the Acoustical Society of Korea
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• v.14 no.2E
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• pp.91-97
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• 1995

This paper describes the implementation of a multi-channel audio codec for HETV. This codec has the features of the 3/2-stereo plus low frequency enhancement, downward compatibility with the smaller number of channels, backward compatibility with the existing 2/0-stereo system(MPEG-1 audio), and multilingual capability. The encoder of this codec consists of 6-channel analog audio input part with the sampling rate of 48 kHz, 4-channel digital audio input part and three TMS320C40 /DSPs. The encoder implements multi-channel audio compression using a human perceptual psychoacoustic model, and has the bit rate reduction to 384 kbit/s without impairment of subjective quality. The decoder consists of 6-channel analog audio output part, 4-channel digital audio output part, and two TMS320C40 DSPs for a decoding procedure. The decoder analyzes the bit stream received with bit rate of 384 kbit/s from the encoder and reproduces the multi-channel audio signals for analog and digital outputs. The multi-processing of this audio codec using multiple DSPs is ensured by high speed transfer of date between DSPs through coordinating communication port activities with DMA coprocessors. Finally, some technical considerations are suggested to realize the problem of real-time operation, which are found out through the implementation of this codec using the MPEG-2 layer II sudio coding algorithm and the use of the hardware architecture with commercial multiple DSPs.