• 대한전기학회논문지
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• 제43권6호
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• pp.951-957
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• 1994

We present a new model for the series resistance of inverted-staggered amorphous silicon (a-Si) thin film transistors (TFT's) by employing the current spreading under the source and the drain contacts as well as the space charge limited current model. The calculated results based on our model have been in good agreements with the measured data over a wide range of applied voltage, gate-to-source and gate-to-drain overlap length, channel length, and operating temperature. Our model shows that the contribution of the series resistances to the current-voltage (I-V) characteristics of the a-Si TFT in the linear regime is more significant at low drain and high gate voltages, for short channel and small overlap length, and at low operating temperature, which have been verified successfully by the experimental measurements.

• 대한전기학회논문지
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• 제43권7호
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• pp.1121-1127
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• 1994

The accelerated degradation phenomena in amorphous silicon thin film transistors due to both electrical stress and visible light illumination under the elevated temperature have been investigated systematically as a function of gate bias, light intensity, and stress time. It has been found that, in case of electrical stress, the thrshold voltage shifts of a-Si:H TFT's may be attributed to the defect creation process at the early stage, while the charge trapping phenomena may be dominant when the stressing periods exceed about 2 hours. It has been also observed that the degradation in the device characteristics of a-Si:H TFT's is accelerated due to multiple stress effects, where the defect creation mechanism may be more responsible for the degradation rather than the charge trapping mechanism.

• 대한전기학회논문지
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• 제41권7호
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• pp.760-765
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• 1992

The material properties and the TFT characteristics fabricated on SiOS12T substrate by LPCVD using SiHS14T gas were investigated. The deposition rate showed Arrhenius behavior with an activation energy of 31Kcal/mol. And the transition temperature form amorphous to crystalline deposition was observed at 570$^{\circ}C$-580$^{\circ}C$. The strong(220) texture was observed as the deposition temperature increases. XRD analysis showed that the film texture of the as-deposited polycrystalline silicon does not change after annealing at 850$^{\circ}C$. The fabricated TFT's based on the as-deposited amorphous film showed superior electrical characteristics to those of the as-deposited polycrystalline films. It is considered that the different electrical characteristics result from the difference of flat band voltage(VS1FBT) due to the interface trap density between the gate oxide and the active channel.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1991년도 추계학술대회 논문집 학회본부
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• pp.257-260
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• 1991

The current-voltage characteristics of inverted-ataggered type a-Si TFT has been successfully obtained by 2-D simulation using Finite Difference Method. Potential and charge distibutions in a-Si TFT's has been calculated by considering localized states in the forbidden gap. The results of numerical simulation have good agreement with the our experimental data.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2003년도 추계학술발표강연 및 논문개요집
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• pp.190-190
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• 2003

현재 a-Si TFT는 평판 디스플레이 소자로서 주로 사용되고 있으나 점차 고속응답속도 특성, 고화질이 요구됨에 따라 높은 전계효과 이동도를 가진 poly-Si TFT로 대체하기 위한 연구가 진행되고 있으며 특히 poly-Si TFT를 상용 유리 기판에 적용하기 위해 비정질 실리콘의 저온 결정화에 대한 연구가 활발히 진행 되고 있다. 본 연구에서는 극박막의 Ni을 선택적으로 증착하여 전계 유도방향성 결정화 (Field Aided Lateral Crystallization : FALC) 공정을 이용하여 결정화를 진행하였으며 전계를 인가하지 않은 경우와 전계를 인가한 경우, 전계 세기에 따른 결정화에 대하여 비교하였다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.20-23
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• 2008

We proposed a-Si:H TFT (hydrogenated amorphous silicon thin film transistor) level shifter which reduced number of power sources. To reduce the number of power sources from four to two, modified bootstrapped inverter was used for the level shifter. The shift register was verified by PSPICE circuit simulation and fabricated. The fabricated level shifter successfully shifted low input (0 to 5 V) to high level output (-7 to 23 V).

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1996년도 춘계학술대회 논문집
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• pp.102-104
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• 1996

The fabrication and analytical expression for the temperature dependent capacitance characteristics of inverted staggered hydrogenerated amorphous silicon thin film transistors(a-si :H TFT) from 303k to 363k were presented. The results show that the experimental capacitance-voltage characteristics at several temperatures are easily measured. Capacitance increased exponentially by gate voltage increase and decreased by temperature increase. C/C(max) ratio decreased at higher temperature, C/C(min) ratio increased at higher temperature.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.I
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• pp.697-699
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• 2005

The need for low cost flexible TFT display backplanes has focused attention on new processing techniques and materials. We have developed backplane technology based entirely on jet-printing, using a combination of additive and subtractive processing, and have applied this technique to both amorphous silicon and polymer TFT arrays.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.205-207
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• 2008

The new process for hybrid silicon thin film transistor (TFT) using DPSS laser has been developed for realizing both low-temperature poly-Si (LTPS) TFT and a-Si:H TFT on the same substrate as a backplane of active matrix liquid crystal display. LTPS TFTs are integrated on the peripheral area of the panel for gate driver integrated circuit and a-Si:H TFTs are used as a switching device for pixel in the active area. The technology has been developed based on the current a-Si:H TFT fabrication process without introducing ion-doping and activation process and the field effect mobility of $4{\sim}5\;cm^2/V{\cdot}s$ and $0.5\;cm^2/V{\cdot}s$ for each TFT was obtained. The low power consumption, high reliability, and low photosensitivity are realized compared with amorphous silicon gate driver circuit and are demonstrated on the 14.1 inch WXGA+ ($1440{\times}900$) LCD Panel.

• 대한전자공학회논문지
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• 제26권3호
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• pp.130-136
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• 1989

보론이 도우핑된 수소화된 비정질 실리콘을 이용한 박막 트랜지스터를 플라즈마 CVD 방법으로 제작하여 트랜지스터의 특성 및 준안정성에 관한 연구를 수행하였다. 보론이 도우핑된 비정질 실리콘 ambipolar 트랜지스터를 열평형 온도 이상에서 급냉하면, active dopants가 증가하고 경계면 상태밀도가 감소하여 정공채널에 의한 드레인 전류가 증가하고 전자채널의 드레인 전류는 급냉 온도에 따라 증가하다 감소되는 현상을 측정하였다. 이런 급냉 효과는 실리콘내에 있는 수소의 운동과 밀접한 관계가 있고 active dopants, 댕글링 본드 및 경계면 상태밀도의 변화로 해석된다.