• Journal of the Korean Vacuum Society
• /
• v.4 no.1
• /
• pp.77-84
• /
• 1995

LCD용 다결정 실리콘 TFT의 제조에 요구되는 고품위의 다결정 실리콘 박막을 60미만의 저온 공정으로 제조하는 기술로 비정질 박막의 고상 결정화(solid phase crystallization) 가 유망하다. 본 연구에서는 고진공 화학증착기를 이용하여 증착된 비정질 실리콘 막의 고상결정거동에 대해 연구하였다. 고상 결정화 속도 및 결정화 후의 결정성(결정립 크기 및 결함 밀도) 화학증착시의 증착가스의 종류(SiH4 혹은 Si2H6), 공정 압력, 증착 온도 등에 민감한 영향을 받으며 Si2H6가스의 사용, 증착 압력의 증가, 증착온도의 감소는 최종 결정립의 크기를 현저히 증가시킨다. 또한 증착전의 기초 진공도를 높임으로써 반응기 잔류 가스에 의한 산소나 탄소 등의 막내 유입이 감소되어 결정화 속도가 증가하고 결정성이 향상되었다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1995.11a
• /
• pp.118-121
• /
• 1995

Fabrication and a new analytical expression for the capacitance characteristics of hydrogenerated amorphous silicon thin film transistors(a-Si:H TFTs) is presented and experimentally verified. The results show that the experimental capacitance characteristics are easily measeured. Measured transfer and DC output characteristic curves of a-Si:H TFT are similar to those of the standard MOSFET-IC. The capacitances on bias voltages are in good agreement with experimental data. This capacitance characteristics is suitable for incorporation into a circuit simulator and can be used for computer-aided design of a-Si thin film transistor integrated circuits.

• Journal of Information Display
• /
• v.7 no.1
• /
• pp.35-40
• /
• 2006

Organic light-emitting diode (OLED) display panel using the charge-pump (CP) pixel addressing scheme was fabricated, and the results show that it is applicable for information display. A CP-OLED panel with 64 ${\times}$ 64 pixels consisting of thin-film capacitors and amorphous silicon Schottky diodes was fabricated using conventional thin-film processes. The pixel drive circuit passes electrical current into the OLED cell during most of the frame period as in the thin-film transistor (TFT)-based active-matrix (AM) OLED displays. In this study, the panel was operated at a voltage level of below 4 V, and this operation voltage can be reduced by eliminating the overlap capacitance between the column bus line and the common electrode.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2005.07b
• /
• pp.1119-1122
• /
• 2005

A selective deposition of Co thin films for thin film transistor gate electrode has been carried out by the growth with combination of micro-contact printing and metal organic chemical vapor deposition (MOCVD). This results in the elimination of optical lithography process. MOCVD has been employed to selectively deposit Co films on preformed OTS gate pattern by using micro-contact printing (${\mu}CP$). A hydrogenated amorphous silicon TFT with a Co gate selectively formed on SAMs patterned structure exhibited a subthreshold slope of 0.88V/dec, and mobility of $0.35cm^2/V-s$, on/off current ratio of $10^6$, and a threshold voltage of 2.5V, and thus demonstrating the successful application of the novel bottom-up approach into the fabrication of a-Si:H TFTs.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.25 no.8
• /
• pp.580-583
• /
• 2012

The dependency of processing pressure on the electrical performances in amorphous silicon-zinc-tin-oxide thin film transistors (SZTO-TFT) has been investigated. The SZTO channel layers were deposited by using radio frequency (RF) magnetron sputtering method with different partial pressure. The field effect mobility (${\mu}_{FE}$) increased and threshold voltage ($V_{th}$) shifted to negative direction with increasing pressure during deposition processing. As a result, oxygen vacancies generated in SZTO channel layer with increasing partial pressure resulted in negative shift in $V_{th}$ and increase in on-current.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2009.10a
• /
• pp.378-381
• /
• 2009

As a Joule-heat source, a conductive Mo layer was used to crystallize amorphous silicon for AMOLED backplanes. This Joule-heating induced crystallization (JIC) process could produce poly-Si having a grain size ranging from tens of nanometers to greater than several micrometers. Here, the blanket (single-shot whole-plane) crystallization could be achieved on the $2^{nd}$ and the $4^{th}$ generation glass substrate.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2000.02a
• /
• pp.186-186
• /
• 2000

After LeComber et al. reported the first amorphous hydrogenated silicon (a-Si: H) TFT, many laboratories started the development of an active matrix LCDs using a-Si:H TFTs formed on glass substrate. With increasing the display area and pixel density of TFT-LCD, however, high mobility TFTs are required for pixel driver of TF-LCD in order to shorten the charging time of the pixel electrodes. The most important of these drawbacks is a-Si's electron mobiliy, which is the speed at which electrons can move through each transistor. The problem of low carier mobility for the a-Si:H TFTs can be overcome by introducing polycrystalline silicon (poly-Si) thin film instead of a-Si:H as a semiconductor layer of TFTs. Therefore, poly-Si has gained increasing interest and has been investigated by many researchers. Recnetly, fabrication of such poly-Si TFT-LCD panels with VGA pixel size and monolithic drivers has been reported, . Especially, fabricating poly-Si TFTs at a temperature mach lower than the strain point of glass is needed in order to have high mobility TFTs on large-size glass substrate, and the monolithic drivers will reduce the cost of TFT-LCDs. The conventional methods to fabricate poly-Si films are low pressure chemical vapor deposition (LPCVD0 as well as solid phase crystallization (SPC), pulsed rapid thermal annealing(PRTA), and eximer laser annealing (ELA). However, these methods have some disadvantages such as high deposition temperature over $600^{\circ}C$, small grain size (<50nm), poor crystallinity, and high grain boundary states. Therefore the low temperature and large area processes using a cheap glass substrate are impossible because of high temperature process. In this study, therefore, we have deposited poly-Si thin films on si(100) and glass substrates at growth temperature of below 40$0^{\circ}C$ using newly developed high rate magnetron sputtering method. To improve the sputtering yield and the growth rate, a high power (10~30 W/cm2) sputtering source with unbalanced magnetron and Si ion extraction grid was designed and constructed based on the results of computer simulation. The maximum deposition rate could be reached to be 0.35$\mu$m/min due to a high ion bombardment. This is 5 times higher than that of conventional sputtering method, and the sputtering yield was also increased up to 80%. The best film was obtained on Si(100) using Si ion extraction grid under 9.0$\times$10-3Torr of working pressure and 11 W/cm2 of the target power density. The electron mobility of the poly-si film grown on Si(100) at 40$0^{\circ}C$ with ion extraction grid shows 96 cm2/V sec. During sputtering, moreover, the characteristics of si source were also analyzed with in situ Langmuir probe method and optical emission spectroscopy.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2013.02a
• /
• pp.543-543
• /
• 2013

Thin-film transistors (TFTs) based on oxide semiconductors have been regarded as promising alternatives for conventional amorphous and polycrystalline silicon TFTs. Oxide TFTs have several advantages, such as low temperature processing, transparency and high field-effect mobility. Lots of oxide semiconductors for example ZnO, SnO2, In2O3, InZnO, ZnSnO, and InGaZnO etc. have been researched. Particularly, zinc-tin oxide (ZTO) is suitable for channel layer of oxide TFTs having a high mobility that Sn in ZTO can improve the carrier transport by overlapping orbital. However, some issues related to the ZTO TFT electrical performance still remain to be resolved, such as obtaining good electrical contact between source/drain (S/D) electrodes and active channel layer. In this study, the bottom-gate type ZTO TFTs with staggered structure were prepared. Thin films of ZTO (40 nm thick) were deposited by DC magnetron sputtering and performed at room temperature in an Ar atmosphere with an oxygen partial pressure of 10%. After annealing the thin films of ZTO at $400^{\circ}C$ or an hour, Cu, Mo, ITO and Ti electrodes were used for the S/D electrodes. Cu, Mo, ITO and Ti (200 nm thick) were also deposited by DC magnetron sputtering at room temperature. The channel layer and S/D electrodes were defined using a lift-off process which resulted in a fixed width W of 100 ${\mu}m$ and channel length L varied from 10 to 50 ${\mu}m$. The TFT source/drain series resistance, the intrinsic mobility (${\mu}i$), and intrinsic threshold voltage (Vi) were extracted by transmission line method (TLM) using a series of TFTs with different channel lengths. And the performances of ZTO TFTs were measured by using HP 4145B semiconductor analyzer. The results showed that the Cu S/D electrodes had a high intrinsic field effect mobility and a low effective contact resistance compared to other electrodes such as Mo, ITO and Ti.

• Journal of Sensor Science and Technology
• /
• v.2 no.1
• /
• pp.95-99
• /
• 1993

a-Si : H TFTs for image sensor have been fabricated and their operational characteristics have been investigated. Hydrogenated amorphous silicon nitride(a-SiN : H) films were used for the gate insulator and $n^{+}$-a-Si : H films were depostied for the source and drain contact. The thicknesses of a-SiN : H and a-Si : H films were $2000{\AA}$, respectively and the thickness of $n^{+}$-a-Si : H film was $500{\AA}$. Also the channel length and channel width of a-Si : H TFTs were $50{\mu}m$ and $1000{\mu}m$, respectively. The ON/OFF current ratio, threshold voltage, and field effect mobility of fabricated a-Si : H TFTs were $10^{5}$, 6.3 V, and $0.15cm^{2}/V{\cdot}s$, respectively.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.9 no.2
• /
• pp.303-310
• /
• 2008

We fabricated hydrogenated amorphous silicon(a-Si:H) 140 nm thick film on a $180\;nm-SiO_2/Si$ substrate with an inductively-coupled plasma chemical vapor deposition(ICP-CVD) equipment at $250^{\circ}C$. Moreover, 30 nm-Ni film was deposited with a thermal-evaporator sequently. Then the film stack was annealed to induce silicides by a rapid thermal annealer(RTA) at $200{\sim}500^{\circ}C$ in every $50^{\circ}C$ for 30 minuets. We employed a four-point tester, high resolution X-ray diffraction(HRXRD), field emission scanning electron microscope(FE-SEM), transmission electron microscope(TEM), and scanning probe microscope(SPM) in order to examine the sheet resistance, phase transformation, in-plane microstructure, cross-sectional microstructure evolution, and surface roughness, respectively. We confirmed that nano-thick high resistive $Ni_3Si$, mid-resistive $Ni_2Si$, and low resistive NiSi phases were stable at the temperature of <300, $350{\sim}450^{\circ}C$, and >$450^{\circ}C$, respectively. Through SPM analysis, we confirmed the surface roughness of nickel silicide was below 12 nm, which implied that it was superior over employing the glass and polymer substrates.