• Journal of Information Display
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• 제6권3호
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• pp.12-17
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• 2005

The need for low cost, flexible, thin film transistor (TFT) display backplanes has focused attention on new processing techniques and materials. We report the development of TFT backplane technology based entirely on jet-printing, using a combination of additive and subtractive processing, to print active materials or etch masks. The technique eliminates the use of photolithography and has the potential to reduce the array manufacturing cost. The printing technique is demonstrated with both amorphous silicon and polymer semiconductor TFT arrays, and we show results of small prototype displays.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 한국전기전자재료학회 1993년도 춘계학술대회 논문집
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• pp.96-99
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• 1993

Electrical properties of the Thin Film Transistor(TFT) electrode metal films were investigated through the Test Elements Group(TEG) experiment. The main purpose of this investigation was to characterize the electrical resistance properties of patterned metal films with respect to the variations of film thickness and TEG metal line width. Aluminum(Al), Tantalum(Ta) and Chromium(Cr) that are currently used as TFT electrode films were selected as the probed metal films. To date, no work in the electrical characterizations of patterned electrodes of a-Si TFT was accomplished. Bulk resistance$(R_b)$, sheet resistance$(R_s)$, and resistivities($\rho$) of TEG patterned metal lines were obtained. Electrical continuity test of metal film lines was also performed in order to investigate the stability of metallization process. Almost uniform-linear variations of the electrical properties with respect to the metal line displacements was also observed.

• Proceedings of the KIEE Conference
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• 대한전기학회 2006년도 제37회 하계학술대회 논문집 C
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• pp.1295-1296
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• 2006

수소화된 비정질 실리콘 박막 트랜지스터(a-Si:H TFT)의 이력 현상이 능동형 유기 발광 다이오드(Active-Matrix Organic Light Emitting Diode) 디스플레이 패널을 구동할 경우에, 발생할 수 있는 잔상(Residual Image) 문제를 단위 소자 및 회로에서 실험을 통하여 규명하였다. 게이트 시작 전압을 바꾸어 VGS-ID 특성을 측정할 경우, 게이트 시작 전압이 5V에서 시작한 VGS-ID 곡선이 10V에서 시작한 VGS-ID 곡선에 비해 왼쪽으로 0.15V 이동하였다. 이러한 결과는 게이트 시작 전압의 차이에 의해 발생한 트랩된 전하량(Trapped Charge) 변화로 설명할 수 있다. 또한, 인가하는 게이트 전압 간격을 0.5V에서 0.05V로 감소시켰을 때 전하 디트래핑 비율의 변화(Charge De-trapping Rate)로 인하여, 이력 현상(Hysteresis Phenomenon)으로 인한 단위 소자에서의 문턱전압의 변화가 0.78V에서 0.39V로 감소함을 관찰하였다. 제작된 2-TFT 1-Capacitor의 ANGLED 화소에서 (n-1)번째 프레임에서의 OLED 전류가 (n)번째 프레임에서의 OLED 전류에 35%의 전류오차를 발생시키는 것을 측정 및 분석하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.450-451
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• 2008

Amorphous silicon Solar cell has n-i-p structure in general, and each layer's thickness and doping concentration are very important factors which are as influential on efficiency of salar cell. Using AFORS HET simulation to get the high efficiency, by adjusting n layer's thickness and doping concentration, p layer's doping concentration. The optimized values are a-Si:H(n)'s thickness of 1nm, a-Si:H(n)r's doping concentration of $2\times10^{20}cm^{-3}$, a-Si:H(p+)r's doping concentration of $1\times10^{19}cm^{-3}$. After optimization, the solar cell shows $V_{oc}$=679.5mV, $J_{sc}$=39.02mA/$cm^2$, FF=83.71%, and a high Efficiency=22.21%. Though this study, we can use this study for planning or manufacturing solar cell which has high efficiency.

• Transactions on Electrical and Electronic Materials
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• 제11권5호
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• pp.234-237
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• 2010

Nanoenergetic materials were synthesized and the thermite reaction between the CuO nanowires and the deposited nano-Al by Joule heating was studied. CuO nanowires were grown by thermal annealing on a glass substrate. To produce nanoenergetic materials, nano-Al was deposited on the top surface of CuO nanowires. The temperature of the first exothermic reaction peak occurred at approximately $600^{\circ}C$. The released heat energy calculated from the first exothermic reaction peak in differential scanning calorimetry, was approximately 1,178 J/g. The combustion of the nanoenergetic materials resulted in a bright flash of light with an adiabatic frame temperature potentially greater than $2,000^{\circ}C$. This thermite reaction might be utilized to achieve a highly reliable selective area crystallization of amorphous silicon films.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.343-344
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• 2008

A surface micromachined uncooled microbolometer based on the amorphous silicon was designed, fabricated, and characterized. We designed the microbolometer with a pixel size of $44\times44{\mu}m^2$ and a fill factor of about 50 % ~ 70% by considering such important factors as the thermal conductance, thermal time constant, the temperature coefficient of resistance, and device resistance. Also, we successfully fabricated the microbolometer by using surface MEMS technology. Finally, we investigated responsivity and detectivity properties depends on the active area size.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권3호
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• pp.367-374
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• 2016

This paper presents an electro-thermal modeling of an amorphous silicon (a-Si) uncooled microbolometer. This modeling provides a comprehensive solution for simulating the electro-thermal characteristics of the fabricated microbolometer and enables electro-thermal co-simulation between MEMS and CMOS integrated circuits. To validate this model, three types of uncooled microbolometers were fabricated using a post-CMOS surface micromachining process. The simulation results show a maximum discrepancy of 2.6% relative to the experimental results.

• Transactions on Electrical and Electronic Materials
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• 제18권3호
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• pp.141-143
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• 2017

Novel structured thin film transistors (TFTs) of amorphous silicon zinc tin oxide (a-SZTO) were designed and fabricated with a thin metal layer between the source and drain electrodes. A SZTO channel was annealed at $500^{\circ}C$. A Ti/Au electrode was used on the SZTO channel. Metals are deposited between the source and drain in this novel structured TFTs. The mobility of the was improved from $14.77cm^2/Vs$ to $35.59cm^2/Vs$ simply by adopting the novel structure without changing any other processing parameters, such as annealing condition, sputtering power or processing pressure. In addition, stability was improved under the positive bias thermal stress and negative bias thermal stress applied to the novel structured TFTs. Finally, this novel structured TFT was observed to be less affected by back-channel effect.

• Journal of Information Display
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• 제9권4호
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• pp.21-29
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• 2008

We studied both the wavelength and intensity dependent photo-responses (photofield-effect) in amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs). During the a-IGZO TFT illumination with the wavelength range from $460\sim660$ nm (visible range), the off-state drain current $(I_{DS_off})$ only slightly increased while a large increase was observed for the wavelength below 400 nm. The observed results are consistent with the optical gap of $\sim$3.05eV extracted from the absorption measurement. The a-IGZO TFT properties under monochromatic illumination ($\lambda$=420nm) with different intensity was also investigated and $I_{DS_off}$ was found to increase with the light intensity. Throughout the study, the field-effect mobility $(\mu_{eff})$ is almost unchanged. But due to photo-generated charge trapping, a negative threshold voltage $(V_{th})$ shift is observed. The mathematical analysis of the photofield-effect suggests that a highly efficient UV photocurrent conversion process in TFT off-region takes place. Finally, a-IGZO mid-gap density-of-states (DOS) was extracted and is more than an order of magnitude lower than reported value for hydrogenated amorphous silicon (a-Si:H), which can explain a good switching properties observed for a-IGZO TFTs.

• Journal of the Korean Institute of Telematics and Electronics A
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• 제30A권8호
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• pp.34-41
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• 1993

Effect of high temperature annealing conditions on Ta$_{2}O_{5}$ thin films was investigated. Ta$_{2}O_{5}$ thin films were deposited on P-type silicon substrates by plasma-enhanced chemical vapor deposition (PECVD) using tantalum ethylate. Ta(C$_{2}H_{5}O)_{5}$, and nitrous oxide. N$_{2}$O. The microstructure changed from amorphous to polycrystalline above 700.deg. C annealing temperature. The refractive index, dielectric onstant and leakage current of the film increased as annealing temperature increased. However, annealing in oxygen ambient reduced leakage currents and dielectric constant due to the formation of interfacial SiO$_{2}$ layer. By optimizing annealing temperature and ambient, leakage current lower than 10$^{-8}$ A/cm$^{2}$ and maximum capacitance of 9 fF/${\mu}m^{2}$ could be obtained.