• 조명전기설비학회논문지
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• 제23권2호
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• pp.45-52
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• 2009

본 연구는 Full-HD급 PDP의 고속 구동 구현을 위한 새로운 구동 방식에 관한 연구이다. 새로운 SPA (self-priming address) 구동 파형은 어드레스 구간에서 지속적인 프라이밍 방전을 유지하여 하전 입자 효과를 이용하여 어드레스 방전 지연 시간을 개선하기 위하여 제안되었다. 본 연구에서는 프라이밍 방전의 기본 특성에 대해 조사하였으며, 안정적인 프라이밍 방전을 유지할 수 있는 초기화 펄스 및 프라이밍 램프 펄스를 도출하였다. 특히, 프라이밍 램프 펄스의 기울기가 0.1[$V/{\mu}s$]의 미약한 프라이밍 방전의 경우에 대해서도 기존 방식의 1.2[${\mu}s$]의 어드레스 방전 지연 시간을 0.8[${\mu}s$]로 획기적으로 개선할 수 있는 것을 확인하였다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2000년도 제1회 학술대회 논문집
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• pp.97-98
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• 2000

This paper deals with the relationship between the addressing and the display in ac-PDP. Especially, deals with the transfer probability of surface discharge according to addressing voltage (Va), blocking voltage(Vg) in addressing period and the characteristics of luminance according to sustain voltage(Vs) in sustaining period with ADS(Address Display period Separation) driving method.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 E
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• pp.2016-2018
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• 1999

Until now, there is no report for the relationship between the condition of addressing and the characteristics of surface discharge in ac- PDP. We have known that such experiments were important to drive a-PDP. Therefore, This paper deals with the probability of transfer and the characteristics of luminance according to addressing voltage (Va), blocking voltage (Vg)in addressing period and sustain voltage(Vs)in sustaining period and we use waveform according to ADS (Address and Display period Separation) method.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 춘계학술대회 논문집
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• pp.391-394
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• 1999

Until now, there is no report for the relationship between the condition of addressing and the characteristics of surface discharge in ac-PDP. We have known that such these experiment was important to drive ac PDP Therefore, this paper deals with the probability of transfer and the character of luminance according to addressing voltage(Va) and blocking voltage(Vg) in addressing period and sustain voltage in sustaining period and we use waveform according to ADS(Address and Display period Separation) method

• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 하계학술대회 논문집 C
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• pp.1815-1817
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• 2000

Plasma display Panels(PDPs) are one of the leading technologies currently under development for large-area high-brightness flat panel displays. However, the luminance and luminous efficiency of at PDPs should be improved. Especially, one of the main factors affecting on the luminance and luminous efficiency of ac PDP may be the phosphor thickness and size of discharge space. In this study, we examined into addressing time, electrical and optical properties as a parameter of the phosphor thickness and the size of discharge space during the display period of ac PDP. It is found out that the optimum phosphor thickness was $50{\mu}m$ and height of discharge space was about $100{\mu}m$.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.I
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• pp.643-646
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• 2005

We present new ramp-reset waveforms that realize fast addressing in AC-PDPs. These waveforms distort the distribution of wall charges on the surface of a phosphor layer: hence, the enhanced electric field helps to ignite a cell faster. They also reduce the black luminance: the divide of erasing ramp down discharges into two parts, i.e. a surface discharge and a vertical discharge, makes lower luminance.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2003년도 International Meeting on Information Display
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• pp.734-738
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• 2003

The addressing time should be reduced by modifying cell and/or driving method in order to replace the dual scan system by single scan and increase the luminance in large ac plasma display panel(PDP). In this paper, the relationships between of discharge cell structure and addressing time in ac PDP are investigated. It is found out that the addressing time was decreased with decreasing gap of ITO electrode and thickness of transparence dielectric layer on the front glass. The decrease rates were 4% per $10{\mu}m$ and 4% per $5{\mu}m$, respectively. Also in cases of decreasing height of barrier rip and thickness of white dielectric layer on the rear glass, addressing times were at the rate of 4% per $10{\mu}m$ and 4% per $2{\mu}m$, respectively.

• Journal of Information Display
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• 제2권1호
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• pp.24-33
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• 2001

The characteristics of the reset and the address discharges of an alternating current Plasma Display Panel (ac PDP) were studied using 2-dimensional numerical discharge cell simulation. We investigated the wall charge variations during the reset discharge adopting ramping reset pulse and the subsequent addressing discharge. The roles of the ramping reset scheme can be divided into two stages, each electrode gathers wall charges during ramping-up of the initial stage and the built-up wall charges are lost during ramping-down of the later stage. Address discharge does not only change the wall charge distributions on the address and the scan electrodes but also on the sustain electrode. The increase in the wall charges on the sustain electrode was observed with the variation of the applied voltage to the sustain electrode during the address period. The increase of the applied voltage to the sustain electrode during the address period is expected to induce the decrease of the sustain voltage during the display period.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 Techno-Fair 및 추계학술대회 논문집 전기물성,응용부문
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• pp.214-215
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• 2007

Unstable sustain discharges can occur at the bottom cells of the panel at high temperature. To solve this phenomenon, the wall charge variation during an address period was investigated. A test panel of 7.5 inch XGA level was used and one green cell was measured. In order to realize operating condition equal to that of the bottom cells of 50 inch panel, the addressing stress pulses are applied. It seems that the resultant wall charge loss during address period increased with increase of temperature as well as the addressing stress pulse voltage. Therefore it results in unstable discharge during sustain period.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.1555-1558
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• 2008

Various approaches were undertaken by major PDP makers in order to improve the luminous efficacy of the plasma discharge cells. There have been many reports that state that using a high Xe content PDP is one of the most promising key technologies available to improve the luminous efficacy. In the case of the higher Xe content panel, the higher address and sustain voltage were needed to drive the panel under the same reset condition. In this study, a variety of Xe content panels were investigated in order to examine wall voltage transfer behaviors. The transferred wall voltage status after addressing discharge at the same driving condition was analyzed by comparing Vt close curve of high and low Xe content panels. Through this analysis of Vt close curve difference, the driving waveform of a high Xe panel was quantitatively adjusted Under the same address voltage condition, results showed that the amount of the transferred wall voltage and Vt close curve after addressing discharge was matched for the first sustain discharge. Taking these results into consideration, we conclude that the driving waveform for different Xe content panels could be designed for the desired addressing discharge condition and the wall voltage state of the cell could be quantitatively controlled and measured through these approaches.