• 제목/요약/키워드: adaptive circuit

검색결과 226건 처리시간 0.031초

An Advanced Coding for Video Streaming System: Hardware and Software Video Coding

  • Le, Tuan Thanh;Ryu, Eun-Seok
    • 인터넷정보학회논문지
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    • 제21권4호
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    • pp.51-57
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    • 2020
  • Currently, High-efficient video coding (HEVC) has become the most promising video coding technology. However, the implementation of HEVC in video streaming systems is restricted by factors such as cost, design complexity, and compatibility with existing systems. While HEVC is considering deploying to various systems with different reached methods, H264/AVC can be one of the best choices for current video streaming systems. This paper presents an adaptive method for manipulating video streams using video coding on an integrated circuit (IC) designed with a private network processor. The proposed system allows to transfer multimedia data from cameras or other video sources to client. For this work, a series of video or audio packages from the video source are forwarded to the designed IC via HDMI cable, called Tx transmitter. The Tx processes input data into a real-time stream using its own protocol according to the Real-Time Transmission Protocol for both video and audio, then Tx transmits output packages to the video client though internet. The client includes hardware or software video/audio decoders to decode the received packages. Tx uses H264/AVC or HEVC video coding to encode video data, and its audio coding is PCM format. By handling the message exchanges between Tx and the client, the transmitted session can be set up quickly. Output results show that transmission's throughput can be achieved about 50 Mbps with approximately 80 msec latency.

Dual EKF-Based State and Parameter Estimator for a LiFePO4 Battery Cell

  • Pavkovic, Danijel;Krznar, Matija;Komljenovic, Ante;Hrgetic, Mario;Zorc, Davor
    • Journal of Power Electronics
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    • 제17권2호
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    • pp.398-410
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    • 2017
  • This work presents the design of a dual extended Kalman filter (EKF) as a state/parameter estimator suitable for adaptive state-of-charge (SoC) estimation of an automotive lithium-iron-phosphate ($LiFePO_4$) cell. The design of both estimators is based on an experimentally identified, lumped-parameter equivalent battery electrical circuit model. In the proposed estimation scheme, the parameter estimator has been used to adapt the SoC EKF-based estimator, which may be sensitive to nonlinear map errors of battery parameters. A suitable weighting scheme has also been proposed to achieve a smooth transition between the parameter estimator-based adaptation and internal model within the SoC estimator. The effectiveness of the proposed SoC and parameter estimators, as well as the combined dual estimator, has been verified through computer simulations on the developed battery model subject to New European Driving Cycle (NEDC) related operating regimes.

파력발전기의 에너지 회생을 위한 연구 (A study on design and modeling of a Wave Energy Converter)

  • 윤종일;안경관;딩광쪙;황후티엔
    • 한국신재생에너지학회:학술대회논문집
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    • 한국신재생에너지학회 2011년도 춘계학술대회 초록집
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    • pp.167.2-167.2
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    • 2011
  • Motions in nature, for example ocean wave, has been playing a significant role for generating electricity production in our modern life. This paper presents an innovative approach for electric power conversion of the vast ocean wave energy. Here, a floating-buoy wave energy converter (WEC) using hydrostatic transmission (HST), which is shortened as HSTWEC, is proposed and designed to enhance the wave energy harvesting task during all wave fluctuations. In this HSTWEC structure, the power take-off system (PTO) is a combination of the designed HST circuit and an electric generator to convert mechanical energy generated by ocean wave into electrical energy. Several design concepts of the HSTWEC have been considered in this study for an adequate investigation. Modeling and simulations using MATLAB/Simulink and AMESim are then carried out to evaluate these design concepts to find out the best solution. In addition, an adaptive controller is designed for improving the HSTWEC performance. The effectiveness of the proposed HSTWEC control system is finally proved by numerical simulations.

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Peak-Valley Current Mode Controlled H-Bridge Inverter with Digital Slope Compensation for Cycle-by-Cycle Current Regulation

  • Manoharan, Mohana Sundar;Ahmed, Ashraf;Park, Joung-Hu
    • Journal of Electrical Engineering and Technology
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    • 제10권5호
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    • pp.1989-2000
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    • 2015
  • In this paper, digital peak current mode control for single phase H-bridge inverters is developed and implemented. The digital peak current mode control is achieved by directly controlling the PWM signals by cycle-by-cycle current limitation. Unlike the DC-DC converter where the output voltage always remains in the positive region, the output of DC-AC inverter flips from positive to negative region continuously. Therefore, when the inverter operates in negative region, the control should be changed to valley current mode control. Thus, a novel control logic circuit is required for the function and need to be analyzed for the hardware to track the sinusoidal reference in both regions. The problem of sub-harmonic instability which is inherent with peak current mode control is also addressed, and then proposes the digital slope compensation in constant-sloped external ramp to suppress the oscillation. For unipolar PWM switching method, an adaptive slope compensation in digital manner is also proposed. In this paper, the operating principles and design guidelines of the proposed scheme are presented, along with the performance analysis and numerical simulation. Also, a 200W inverter hardware prototype has been implemented for experimental verification of the proposed controller scheme.

KOA 기반의 유한체 승산기 설계 (Design of Finite Field Multiplier based on KOA)

  • 변기영;나기수;김흥수
    • 전기전자학회논문지
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    • 제8권1호
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    • pp.1-11
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    • 2004
  • 본 논문에서는 KOA를 적용하여 유한체 승산의 새로운 연산기법을 제시하였다. 먼저, 승산의 전개를 위해 주어진 다항식을 2분 또는 3분하여 각각 2항식과 3항식으로 재구성한 후 정의된 보조다항식을 사용하여 승산을 이루도록 하였다. 승산된 다항식에 모듈러 환원을 적용하기 위해 mod $F({\alpha})$ 연산식을 새롭게 전개하여 제시하였다. 제시된 연산기법들을 적용하여 $GF(2^m)$상의 승산회로를 구성하였고, Parr의 회로와 비교하였다. 비교논문의 경우 $GF((2^4)^n)$을 전제함으로써 그 적용이 매우 제한적이나, 본 논문에서는 $m=2^n$$m=3^n$인 경우를 보임으로써 그 적용이 Parr의 회로에 비해 보다 확장되었다.

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$2GHz{\sim}10GHz$ 무선 채널 환경에서 비례 적응형 등화기를 이용한 SC-FDE 시스템 구현과 성능분석 (Analysis of Performance for SC-FDE Systems Using Proportional Adaptive Equalizer in $2GHz{\sim}10GHz$ Frequency Radio Channel Models)

  • 양용석;이규대
    • 한국통신학회논문지
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    • 제32권4C호
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    • pp.447-453
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    • 2007
  • 다중 경로 페이딩 환경에서 OFDM(Orthogonal frequency Division Multiplexing)방식은 보호 구간 및 주파수영역 등화로 심벌 및 채널 간 간섭을 방지하는 특성을 가지는 반면 전송신호의 PAPR(Peak-to-Average Power Ratio)크다는 것이다. SC-FDE(Single Carrier with Frequency Domain Equalization)방식은 OFDM과 유사한 성능을 가지면서 상대적으로 PAPR이 적은 반면 등화기가 복잡하다. 본 논문에서는 SC-FDE시스템을 위한 주파수영역 비례 적응형 등화기를 제안하고, $2GHz\;{\sim}\;10GHz$ 대역의 다양한 채널모델 환경 하에서 성능을 분석함으로 802.11 및 802.16 등에 효과적으로 적용할 수 있음을 제시하였다. 아울러 동일조건의 OFDM시스템과 성능을 비교하여 수렴속도가 빠르고 단말기의 복잡도를 줄일 수 있음을 시뮬레이션을 통해 증명하였다.

A High-Linearity Low-Noise Reconfiguration-Based Programmable Gain Amplifier

  • Han, Seok-Kyun;Nguyen, Huy-Hieu;Lee, Sang-Gug
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제13권4호
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    • pp.318-330
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    • 2013
  • This paper presents a high-linearity low-noise small-size programmable gain amplifier (PGA) based on a new low-noise low-distortion differential amplifier and a proposed reconfiguration technique. The proposed differential amplifier combines an inverter-based differential pair with an adaptive biasing circuit to reduce noise and distortion. The reconfiguration technique saves the chip size by half by utilizing the same differential pair for the input transconductance and load-stage, interchangeably. Fabricated in $0.18-{\mu}m$ CMOS, the proposed PGA shows a dB-linear control range of 21dB in 16 steps from -11 dB to 10 dB with a gain error of less than ${\pm}0.33$ dB, an IIP3 of 7.4~14.5 dBm, a P1dB of -7~1.2 dBm, a noise figure of 13dB, and a 3-dB bandwidth of 270MHz at the maximum gain, respectively. The PGA occupies a chip area of $0.04mm^2$ and consumes only 1.3 mA from the 1.8 V supply.

${\lambda}/4$ 전송선로를 이용한 부하단 임피던스 측정방법에 관한 연구 (A study of measurement of the unknown load impedance using sectioned transmission line)

  • 황수설;홍성용
    • 한국위성정보통신학회논문지
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    • 제6권2호
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    • pp.91-96
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    • 2011
  • 본 논문에서는 물리적인 환경 변화에 의해 발생될 수 있는 갑작스런 부하단 임피던스의 변화를 정확히 측정할 수 있는 방법을 제시하였다. 부하단 임피던스 측정방법으로 ${\lambda}/4$ 전송선로(Sectioned Transmission Line) 상에서 측정된 전압을 이용하여 임의의 부하단 임피던스를 구하는 수식을 유도하였고, 계산된 수식의 결과 중 유효한 결과 만을 선택하는 부하단 임피던스 결정 알고리즘을 도출하였다. 제안된 임의의 부하단 임피던스 계산 수식과 부하단 임피던스 결정 알고리즘을 다양한 부하단이 적용된 시뮬레이션을 통해 검증하였고, 시뮬레이션 결과를 통해 임의로 설정한 부하단 임피던스를 정확하게 찾아 주는 것을 확인하였다.

단상 PV 인버터용 온라인 데드타임 보상기 연구 (A New On-Line Dead-Time Compensator for Single-Phase PV Inverter)

  • 부우충기엔;이상회;차한주
    • 전력전자학회논문지
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    • 제17권5호
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    • pp.409-415
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    • 2012
  • This paper presents a new software-based on-line dead-time compensation technique for a single-phase grid-connected photovoltaic (PV) inverter system. To prevent a short circuit in the inverter arms, a switching delay time must be inserted in the pulse width modulation (PWM) signals. This causes the dead-time effect, which degrades the system performance around zero-crossing point of the output current. To reduce the dead-time effect around the zero-crossing point of grid current, a harmonic mitigation of grid current is used as an additional part of the synchronous frame current control scheme. This additional task mitigates the harmonic components caused by the dead-time from the grid current. Simulation and experimental results are shown to verify the effectiveness of the proposed dead-time compensation method in the single-phase grid-connected inverter system.

피드백 저항 제어에 의한 무선랜용 가변이득 저전압구동 저잡음 증폭기 MMIC (A Variable-Gain Low-Voltage LNA MMIC Based on Control of Feedback Resistance for Wireless LAN Applications)

  • 김근환;윤경식;황인갑
    • 한국통신학회논문지
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    • 제29권10A호
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    • pp.1223-1229
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    • 2004
  • 본 논문에서 ETRI 0.5$\mu\textrm{m}$ MESFET 라이브러리 공정을 이용하여 동작 주파수 5GHz대 저전압구동 가변이득 저잡음 증폭기 MMIC를 설계 및 제작하였다. 이 저잡음 증폭기는 HIPERLAN/2의 Adaptive Antenna Arrays와 함께 사용할 수 있도록 이득조절이 가능하도록 설계하였다. 가변이득 저잡음 증폭기는 2단 캐스케이드 구조이며, 게이트전압에 따라 채널저항이 제어되는 증가형 MESFET과 저항으로 구성된 부귀환 회로를 제안하였다. 제작된 가변이득 저잡음 증폭기의 측정값은 $V_{DD}$ =1.5V, $V_{GG1}$=0.4V, $V_{GG2}$=0.5V일때 5.5GHz의 중심 주파수, 14.7dB의 소신호 이득, 10.6dB의 입력 반사손실, 10.7dB의 출력 반사손실, 14.4dB의 가변이득, 그리고 잡음지수 2.98dB이다. 또한, 가변이득 저잡음 증폭기는 -19.7dBm의 입력 PldB, -10dBm의 IIP3, 52.6dB의 SFBR, 그리고 9.5mW의 전력을 소비한다.다.다.