• Title/Summary/Keyword: accumulator

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A study of a new combustion chamber with a mixture accumulator (혼합기어큐뮬레이터를 갖춘 신연소실에 관한 연구)

  • 조진호
    • Journal of the korean Society of Automotive Engineers
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    • v.5 no.1
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    • pp.24-31
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    • 1983
  • 혼합기 어큐물레이터를 부착시킨 연소실에 관한 새로운 아이디어를 고찰하였다. "혼합기어큐물 레이터실 (Mixture Accumulator Chamber; MA Chamber)"로 명명한 이 연소실은 점화전 압축 행정중에 부하상태와 관계없이 내부의 가한 기체난류를 일으킬 수 있다. 이러한 기관(MA engine)의 성능과 그 특성을 연구하였다. 그 기관의 베이스기관(base engine)에 비하여 기관압 축비를 증가시킬 수 있고 희박혼합기로서 안정연소를 시킬 수 있음이 확실하다. 있음이 확실하다.

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Study of the Direct Digital Frequency Synthesizer for FHSS in Wireless LAN Systems (무선 LAN 시스템에서 FHSS을 위한 직접형 디지틀 주파수 합성기에 대한 연구)

  • 임세홍;장용수;이완범;김환용
    • Proceedings of the IEEK Conference
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    • 1999.06a
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    • pp.45-48
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    • 1999
  • The demands of WLAN(Wireless Local Area Network) systems increase rapidly in whole society and this phenonenon has been expected that WLAN wi11 substitute for wired-LAN. The FHSS(Frequency Hopped Spread Spectrum) method using the WLAN is changed to the performance of Frequency synthesizer. In this paper, we proposed pipeline-accumulator using ring-counter method instead of constant accumulator that has demerits of size and power consumption. Designed DDFS generated operating frequency of 167MHz and maximum output frequency of 83.5MHz.

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Implementation of SA-DCT using a datapath (데이터패스를 이용한 SA-DCT 구현)

  • 박주현;김영민
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.35C no.5
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    • pp.25-32
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    • 1998
  • In this paper, SA (shape adaptive)-DCT is implemented using a datapath with 4 MACs (multiplication & accumulator). DCT is a well-known bottleneck of real-time video compression using MPEG-like schemes. High-speed pipelined MACs presented here implement real-time DCT. A datapath in this paper executes DCT/IDCT algorithms for QCIF 15fps(frame per second), maximum rate of VLBV(very low bitrte video) in MPEG-4. A 32bit accumulator in a MAC prevents distortion caused by fixed-point process. It can be applied to various operations such as ME (motion estimation) and MC(motion compensation) with a absolutor and a halfer.

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Design Parameter Optimization of Rope Brake System far Elevator (엘리베이터용 로프 브레이크 시스템의 설계변수 최적화에 관한 연구)

  • 윤영환;최명진
    • Transactions of the Korean Society of Machine Tool Engineers
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    • v.10 no.6
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    • pp.85-94
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    • 2001
  • Hydraulic systems of rope brake for elevators are modelled to evaluate design parameters such as cylinder pressure, pis-ton displacement, accumulator capacity, and so on. To assure the results, experiments were performed. The analysis results agree well with the experimental results. The scheme in this study is expected to be utilized in the design of rope brake system for elevators to get design parameters and to improve the safety.

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Accelerated Life Test Design of Bladder Type Accumulator Assembly for Helicopter (헬기용 블래더형 축압기 조립체의 가속수명시험 설계)

  • Kim, Dae-Yu;Hur, Jang-Wook
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.19 no.8
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    • pp.239-245
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    • 2018
  • The importance of reliability in the development of weapons systems and reliability tests has been emphasized recently. Therefore, this study evaluated a reliability test design method of a bladder type accumulator and proposed a process for reliability test design. To design the reliability test of the accumulator, the main failure modes and failure mechanisms were investigated, and the main stress factors were analyzed to select the appropriate acceleration model. A steady - state reliability test was designed according to the number of samples, and the reliability level and accelerated life test time were calculated according to the acceleration factor computed using the selected acceleration model.

Design of a Low Power Consumption Accumulator for Parallel Correlators in Spread Spectrum Systems (대역확산 시스템용 병렬 상관기를 위한 저 전력 누적기 설계)

  • Ryoo, Keun-Jang;Chong, Jong-Wha
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.36C no.12
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    • pp.27-35
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    • 1999
  • In a typical spread spectrum system, parallel correlator occupies a large fraction of power consumption because of the large number of accumulators in the system. In this paper, a novel accumulator is proposed that can reduce the power consumption in the parallel correlator. The proposed accumulator counts the numbers of 1 of the incoming input data. The counted values are weighted and added together to obtain the final correlation value only at the end of the accumulation. The proposed accumulator has been designed and simulated by CADENCE Verilog-XL and synthesized by SYNOPSYS Design Compiler with $0.6{\mu}m$ standard cell library. Power consumption results have been obtained from EPIC PowerMill simulations. Simulation results are very encouraging. First, the power dissipation is reduced by 22% and the maximum operating frequency is increased by 323%. In addition, the parallel correlator using the proposed accumulators consumed less power than the conventional active parallel correlators by 22%, and less power than the conventional passive correlator by 43%.

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A Memory-Efficient Fingerprint Verification Algorithm Using a Multi-Resolution Accumulator Array

  • Pan, Sung-Bum;Gil, Youn-Hee;Moon, Dae-Sung;Chung, Yong-Wha;Park, Chee-Hang
    • ETRI Journal
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    • v.25 no.3
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    • pp.179-186
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    • 2003
  • Using biometrics to verify a person's identity has several advantages over the present practices of personal identification numbers (PINs) and passwords. At the same time, improvements in VLSI technology have recently led to the introduction of smart cards with 32-bit RISC processors. To gain maximum security in verification systems using biometrics, verification as well as storage of the biometric pattern must be done in the smart card. However, because of the limited resources (processing power and memory space) of the smart card, integrating biometrics into it is still an open challenge. In this paper, we propose a fingerprint verification algorithm using a multi-resolution accumulator array that can be executed in restricted environments such as the smart card. We first evaluate both the number of instructions executed and the memory requirement for each step of a typical fingerprint verification algorithm. We then develop a memory-efficient algorithm for the most memory-consuming step (alignment) using a multi-resolution accumulator array. Our experimental results show that the proposed algorithm can reduce the required memory space by a factor of 40 and can be executed in real time in resource-constrained environments without significantly degrading accuracy.

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Development and Evaluation of a Hybrid Damper for Semi-active Suspension (반능동 현가장치의 하이브리드형 댐퍼 개발에 관한 연구)

  • Jin, Chul Ho;Yoon, Young Won;Lee, Jae Hak
    • Journal of Drive and Control
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    • v.15 no.1
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    • pp.38-49
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    • 2018
  • This research describes the development model and testing of a hybrid damper which can be applicable to a vehicle suspension. The hybrid damper is devised to improve the performance of a conventional passive oil damper using a magneto-rheological (MR) accumulator which consists of a gas accumulator and a MR device. The level of damping is continuously variable by the means of control in the applied current in a MR device fitted to a floating piston which separates the gas and the oil chamber. A simple MR device is used to resist the movement of floating piston. At first a mathematical model which describes all flows within the conventional oil damper is formulated, and then a small MR device is also devised and adopted to a mathematical model to characterize the performance of the device.

SIMULATION OF A HYDRAULIC CONTROL SYSTEM FOR POWERSHIFT TRANSMISSION OF TRACTORS

  • Kim, D. C.;Lee, H. S.;Kim, K. U.;Y S. Nam
    • Proceedings of the Korean Society for Agricultural Machinery Conference
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    • 2000.11b
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    • pp.498-505
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    • 2000
  • Performance of a hydraulic system is influenced by its working temperature. Therefore, it is very important to make the system perform uniformly in an entire range of the working temperature. In this study a simulation of a hydraulic control system for the powershift transmission of tractors was conducted and the effect of the temperature was investigated in terms of design conditions of the system. Results of the simulation are as follows. The hydraulic control system with a spring accumulator was found to be more convenient to control the shifting time than that with a gas accumulator. By returning the oil from the clutches to the system through a path between the filter and pump, the time delay due to the pressure difference between the low and high temperatures could be reduced. Therefore, it was recommended that the hydraulic control system for the powershift transmission of tractors must be equipped with a spring accumulator and a circuit to return oil from the clutches to the system through a path between the filter and pump.

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A Digital DLL with 4-Cycle Lock Time and 1/4 NAND-Delay Accuracy

  • Kim, Sung-Yong;Jin, Xuefan;Chun, Jung-Hoon;Kwon, Kee-Won
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.16 no.4
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    • pp.387-394
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    • 2016
  • This paper presents a fully digital delay locked loop (DLL) that can acquire lock in four clock cycles with a resolution of a 1/4 NAND-delay. The proposed DLL with a multi-dither-free phase detector acquires the initial lock in four clock cycles with 1/2 NAND-delay. Then, it utilizes a multi-dither-free phase detector, a region accumulator, and phase blenders, to improve the resolution to a 1/4 NAND-delay. The region accumulator which continuously steers the control registers and the phase blender, adaptively controls the tracking bandwidth depending on the amount of jitter, and effectively suppresses the dithering jitter. Fabricated in a 65 nm CMOS process, the proposed DLL occupies $0.0432mm^2$, and consumes 3.7 mW from a 1.2-V supply at 2 GHz.