• Journal of Positioning, Navigation, and Timing
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• v.12 no.3
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• pp.245-255
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• 2023

Time comparison techniques are necessary for generating and keeping Coordinated Universal Time (UTC) and distributing standard time clocks. Global Navigation Satellite System (GNSS) Common View, GNSS All-in-View, Two-Way Satellite Time and Frequency Transfer (TWSTFT), Very Long Baseline Interferometry (VLBI), optical fiber, and Network Time Protocol (NTP) based methods have been used for time comparison. In these methods, GNSS based time comparison techniques are widely used for time synchronization in critical national infrastructures and in common areas of application such as finance, military, and wireless communication. However, GNSS-based time comparison techniques are vulnerable to jamming or interference environments and it is difficult to respond to GNSS signal disconnection according to the international situation. In response, in this paper, Code-Division Multiple Access (CDMA) based All-to-All TWSTFT operation method is proposed. A software-based simulation platform also was designed for performance analysis in multi-TWSTFT signal environments. Furthermore, code and carrier measurement jitters were calculated in multi-signal environments using the designed simulation platform. By using the technique proposed in this paper, it is anticipated that the TWSTFT-based time comparison method will be used in various fields and satisfy high-performance requirements such as those of a GNSS master station and power plant network reference station.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.5C
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• pp.527-539
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• 2009

In this paper, we propose an asynchonous ICI (Inter-Cell Interference) mitigation techniques for 3GPP LTE MIMO-OFDMA down-link receiver. An increasing in symbol timing misalignments may occur relative to sychronous network as the result of BS (Base Station) timing differences. Such symbol synchronization errors that exceed the guard interval or the cyclic prefix duration may result in MAI (Multiple Access Interference) for other carriers. In particular, at the cell boundary, this MAI becomes a critical factor, leading to degraded channel throughput and severe asynchronous ICI. Hence, many researchers have investigated the interference mitigation method in the presence of asynchronous ICI and it appears that the knowledge of the SCM (Spatial Covariance Matrix) of the asynchronous ICI plus background noise is an important issue. Generally, it is assumed that the SCM estimated by using training symbols. However, it is difficult to measure the interference statistics for a long time and training symbol is also not appropriate for MIMO-OFDMA system such as LTE. Therefore, a noise reduction method is required to improve the estimation accuracy. Although the conventional time-domain low-pass type weighting method can be effective for noise reduction, it causes significant estimation error due to the spectral leakage in practical OFDM system. Therefore, we propose a time-domain sinc type weighing method which can not only reduce the noise effectively minimizing estimation error caused by the spectral leakage but also implement frequency-domain moving average filter easily. By using computer simulation, we show that the proposed method can provide up to 3dB SIR gain compared with the conventional method.

• Journal of IKEEE
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• v.26 no.4
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• pp.633-638
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• 2022

Rencently, neuromorphic systems of spiking neural networks (SNNs) that imitate the human brain have attracted attention. Neuromorphic technology has the advantage of high speed and low power consumption in cognitive applications and processing. Resistive random-access memory (RRAM) for SNNs are the most efficient structure for parallel calculation and perform the gradual switching operation of spike-timing-dependent plasticity (STDP). RRAM as synaptic device operation has low-power processing and expresses various memory states. However, the integration of RRAM device causes high switching voltage and current, resulting in high power consumption. To reduce the operation voltage of the RRAM, it is important to develop new materials of the switching layer and metal electrode. This study suggested a optimized new structure that is the Metal/Al₂O₃/HfO_x/SWCNTs/N+silicon (MOCS) with single-walled carbon nanotubes (SWCNTs), which have excellent electrical and mechanical properties in order to lower the switching voltage. Therefore, we show an improvement in the gradual switching behavior and low-power I/V curve of SWCNTs-based memristors.

• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
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• v.5 no.4
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• pp.45-53
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• 2015

In this paper, an approach of temporal certification system that can be easily added on current character-based certification system is newly introduced. This technique enhances the security of the password certification process by exploiting temporal information for each character's stroke timing, and using them as another feature of certification information, on top of character comparison process. There are three different temporal conditions: maximum, minimum and no-option. The maximum condition along with a time number (usually 0.2 second or less) means that the next key input should be punched within the time limit, while the minimum condition means the next key stroke should be typed after the time lapse specified. With no-option condition chosen, user can punch the password without any timing constraints. Prototype was developed and tested with four number password case. In comparison with 104 cases, this new approach increases the cases more than 10 digits, enhancing the security of the certification process. One big advantage of this new approach is that user can update his/her password only with different timing constraints, still keeping the same characters, that will enhance the security system management efficiency in a very simple way. Figures and pictures along with process flow are included for the validity of the idea.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.8C
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• pp.742-749
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• 2009

In this paper, we propose mitigation techniques using time-domain shortening filter (TSF) and frequency-domain shortening filter (FSF) to overcome inter-block interference (IBn and inter-carrier interference (ICn due to the time difference of arrival (TDoA) and carrier frequency offset (CFO) between downlink and uplink signals from access point (AP) and subscriber station (SS) in synchronous digital duplexing (SDD)/orthogonal frequency division multiple access (OFDMA) systems for indoor wireless communication. The proposed TSF and FSF maximize SIR for shortening in time (SIRST) and SINR for shortening in frequency (SINRSF), respectively, by using channel impulse responses and timing information among stations, obtained from mutual ranging procedure. It is verified by computer simulation that the proposed TSF and FSF reduce effectively the effects of IBI and ICI in the SDD/OFDMA systems.

• Journal of the Korea Society of Computer and Information
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• v.25 no.1
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• pp.63-69
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• 2020

In this paper, we propose an indoor positioning technique using the landmark based on relative Access Point (AP) signal strengths. The absolute values of AP signals are used to conventional indoor positioning technologies, but they may be different because of the difference of the measuring device, the measuring environment, and the timing of the measurements. However, we found the fact that the flow of the AP's RSSI in certain places shows almost constant patterns. Based on theses characteristics, we identify the relative strength between the APs and store the certain places as landmarks where they show certain patterns. Once the deployment of the landmark map is complete, system calculate position of user using the IMU sensor of smartphone and calibrate it with stored landmarks. Our system shows 75.2% improvement over technology that used only sensors, and 39.6% improvement over technology that used landmarks that were selected with absolute values.

• The Journal of the Korea Contents Association
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• v.22 no.3
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• pp.285-295
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• 2022

The purpose of this study is to prepare primary data for providing smooth and systematic rehabilitation sports services by confirming the opinions of instructors experienced in the field of disability sports before the implementation of Article 15 'Rehabilitation sports' of the 'Act on Guarantee of Right to Health and Access to Health Services for Persons with Disabilities. In-depth interviews were conducted as a research method, and qualitative analysis was conducted on the contents of the interview. The in-depth interview is unstructured, allowing disability sports instructor to freely present their opinions on difficulties experienced while operating the program, necessary matters for rehabilitation sports implementation. We transcribed the recording data of the in-depth interview and coded the opinions through the thematic analysis method among qualitative research methods. As a result, the final 104 opinions were used and classified into 9 categories; rehabilitation sports goal, training rehabilitation sports instructor, evaluation items and educational guidelines, relationships with program participants, facilities utilization, effects, the timing of provision, and doctor roles.

• IEIE Transactions on Smart Processing and Computing
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• v.6 no.2
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• pp.133-139
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• 2017

Vehicles have increasingly evolved and become intelligent with convergence of information and communications technologies (ICT). Vehicle communications (VC) has become one of the major necessities for intelligent vehicles. However, VC suffers from serious security problems that hinder its commercialization. Hence, the IEEE 1609 Wireless Access Vehicular Environment (WAVE) protocol defines a security service for VC. This service includes Advanced Encryption Standard-Counter with CBC-MAC (AES-CCM) for data encryption in VC. A high-speed AES-CCM crypto module is necessary, because VC requires a fast communication rate between vehicles. In this study, we propose and implement an efficient AES-CCM hardware architecture for high-speed VC. First, we propose a 32-bit substitution table (S_Box) to reduce the AES module latency. Second, we employ key box register files to save key expansion results. Third, we save the input and processed data to internal register files for secure encryption and to secure data from external attacks. Finally, we design a parallel architecture for both cipher block chaining message authentication code (CBC-MAC) and the counter module in AES-CCM to improve performance. For implementation of the field programmable gate array (FPGA) hardware, we use a Xilinx Virtex-5 FPGA chip. The entire operation of the AES-CCM module is validated by timing simulations in Xilinx ISE at a speed of 166.2 MHz.

• ETRI Journal
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• v.28 no.4
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• pp.475-485
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• 2006

Network-on-chip (NoC) is an emerging design paradigm intended to cope with future systems-on-chips (SoCs) containing numerous built-in cores. Since NoCs have some outstanding features regarding design complexity, timing, scalability, power dissipation and so on, widespread interest in this novel paradigm is likely to grow. The test strategy is a significant factor in the practicality and feasibility of NoC-based SoCs. Among the existing test issues for NoC-based SoCs, test access mechanism architecture and test scheduling particularly dominate the overall test performance. In this paper, we propose an efficient NoC-based SoC test scheduling algorithm based on a rectangle packing approach used for current SoC tests. In order to adopt the rectangle packing solution, we designed specific methods and configurations for testing NoC-based SoCs, such as test packet routing, test pattern generation, and absorption. Furthermore, we extended and improved the proposed algorithm using multiple test clocks. Experimental results using some ITC'02 benchmark circuits show that the proposed algorithm can reduce the overall test time by up to 55%, and 20% on average compared with previous works. In addition, the computation time of the algorithm is less than one second in most cases. Consequently, we expect the proposed scheduling algorithm to be a promising and competitive method for testing NoC-based SoCs.