• Journal of Korea Society of Industrial Information Systems
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• v.18 no.5
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• pp.51-58
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• 2013

A clock duty-cycle corrector (DCC) which is an essential device of clocking circuits for high-speed system-on-chip (SoC) design is introduced in this paper. The architectures and operation of conventional analog feedback DCCs and digital feedback DCCs are compared and analyzed. A new mixed-mode feedback DCC that combines the advantages of analog DCCs and digital DCCs to achieve a wider duty-cycle correction range, higher operating frequency, and higher duty-cycle correction accuracy is presented. Especially, the architectures and design of a mixed-mode duty-cycle amplifier (DCA) which is a core unit circuit of a mixed-mode DCC is presented in detail. Two mixed-mode DCCs based on a single-stage DCA and a two-stage DCA were designed in a 0.18-${\mu}m$ CMOS process, and it is proven that the two-stage DCA-based DCC has a wider duty-cycler correction range and smaller duty-cycle correction error.

• Journal of Power Electronics
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• v.16 no.2
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• pp.621-630
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• 2016

In this paper, a single current sensor technique (SCST) is proposed for single-phase full-bridge inverters. The proposed SCST measures the currents of multiple branches at the same time, and reconstructs the average inductor, capacitor, and load current in a single switching cycle. Since all of the branches' current in the LC filter and the load are obtained using the SCST, both the inductor and the capacitor current feedback schemes can be selectively applied while taking advantages of each other. This paper also analyzes both of the current feedback schemes from the view point of the closed-loop output impedance. The proposed SCST and the analysis in this paper are verified through experiments on a 3kVA single-phase uninterruptible power supply (UPS).

• Transactions of the Korean Society of Mechanical Engineers A
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• v.23 no.7 s.166
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• pp.1164-1172
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• 1999

In this study, to investigate the fatigue crack retardation behavior and the variability of retardation cycles, fatigue crack growth tests were conducted on 7075-T6 aluminum alloy under single tensile overload. A retardation coefficient, D was introduced to describe fatigue crack retardation behavior and a random variable, Z to describe the variability of fatigue crack growth. The retardation coefficient was separately formulated according to retardation behavior which is composed of delayed retardation part and retardation part. The random variable, Z was evaluated from experimental data which was obtained from fatigue crack growth tests under constant amplitude load. Using these variables, a probabilistic model was developed on the basis of the modified Forman's equation, and retardation behavior and cycles were predicted under certain overload condition. The predicted retardation curve well agrees with the trend of experimental crack retardation behavior. And this model well predicts the scatter of experimental retardation cycles.

• Journal of Korean Institute of Industrial Engineers
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• v.15 no.2
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• pp.1-10
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• 1989

This paper deals with a single-facility multiproduction model concerning the basic cyclic scheduling. The aim is to obtain the production order of each product in a cycle and the cycle frequency for minimizing the setup costs and inventory carrying costs of all products. The problem is formulated by LP and it shows that the optimal solution derived dominates the solution of non-cyclic scheduling model on some conditions.

• ALGAE
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• v.25 no.4
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• pp.187-195
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• 2010

The genus Rosenvingea is well known in the tropics. Four species have been reported from Pacific Mexico: R. floridana, R. antillarum, R. intricata and R. sanctae-crucis. We collected a plant (Boca del Cielo, Chiapas) that we identified as Rosenvingea orientalis, a species not previously reported from Pacific Mexico. We were able to characterize the life cycle of this species for the first time in laboratory culture. It reproduced exclusively by plurilocular sporangia (plurangia). The mature plants were up to 6 cm long with cylindrical to compressed fronds (to 2 mm wide) with dichotomous branches in the upper half of the thallus. The medulla was hollow with 2-3 layers of large inflated colourless cells at the periphery. The cortex was comprised of 1 layer of small cells, each with a single chloroplast and pyrenoid. Linear plurangial sori with phaeophycean hairs formed along the mature fronds. Zoospore germlings developed into prostrate filamentous systems, each with a single phaeophycean hair that gave rise to a single erect shoot with multiple hairs arising near the tip. Molecular phylogeny using the psaA gene placed this isolate within the Scytosiphonaceae. It does not confirm the exact identification of R. orientalis, although its placement close to other Rosenvingea sequences was confirmed and morphological evidence supports its placement in R. orientalis. Our culture investigations indicated that it has an asexual life cycle. Further collections are needed to resolve the full generic and specific relationships of Rosenvingea and related taxa, and their reproductive patterns.

• Journal of Internet Computing and Services
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• v.5 no.4
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• pp.35-42
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• 2004

In this paper the more accurate models than any other ones so far have been proposed for the performance evaluation of single-buffered banyan-type Multistage Interconnection Networks(MINs)'s under nonuniform traffic condition is obtained. Small clock cycle instead of big clock cycle is used. The accuracy of proposed models are conformed by comparing with the results from simulation.

• Proceedings of the SAREK Conference
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• 2009.06a
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• pp.533-538
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• 2009

The present study has been conducted to an analysis of two stage refrigeration cycle with alternative refrigerant R410A. In the analysis, single stage cycle (R22 and R410A) compared to COP changing with supercooling degree. Secondly, two stage refrigeration cycle is investigated to the existence of intercooler or supercooler. At results, supercooler contributes to the increase of cooling capacity and the decrease of COP.

• Journal of KSNVE
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• v.8 no.6
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• pp.1144-1149
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• 1998

A two degree-of-freedom model of suspended cables is studied for forced resonant response. The method of averaging is used to obtain first-order approximations to the response of the system. A bifurcation analysis of the averaged system is performed in the case of 2-to-1 internal resonance. Nonlinear coupled-mode motions are found to bifurcate from single-mode responses and further bifurcate to limit cycle motions via Hopf bifurcations. The limit cycle solutions undergo period doubling bifurcations to chaos.

• Proceedings of the KIPE Conference
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• 2018.07a
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• pp.198-200
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• 2018

In this paper a single-stage single-phase differential type isolated AC-DC converter is proposed. This converter eliminates the requirement to use bulky electrolytic capacitor from the system and at the same time provides DC charging by employing the AC Power Decoupling waveform control method. All the switches of the converter achieve ZVS turn on during half line cycle and all diodes achieve ZCS turn off during entire line cycle. A conventional controller is implemented for PFC control and output regulation, whereas a power decoupling controller is added to compensate $2^{nd}$ harmonic ripple power. In addition, an interleaving technique is applied to increase the power range of the converter and reduce the input inductor size. In the end simulation verification is performed and results are obtained for 6.6KW.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.3
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• pp.1-7
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• 2002

This paper presents a new PLL clock generator that can improve a jitter noise characteristics and acquisition process by designing a multi-PFD(Phase Frequency Detector) and an adaptive charge pump circuit. The conventional PLL has not only a jitter noise caused from such a demerit of the wide dead zone and duty cycle, but also a long delay interval that makes a high speed operation unable. An advanced multi-structured PFD circuit using the TSPC(True Single Phase Clocking) circuit is proposed, in which it shows an excellent functionalities in terms of the jitter noises by designing its circuit with the exact dead zone and duty cycle. Our new designed adaptive charge pump in the loop filter of a PLL can improve an acquisition characteristic by adaptively increasing of current. The Hspice simulation is done to evaluate the performance of the proposed circuit. Simulation result shows that our PLL has under 0.01ns in the dead zone, no influence from the duty cycle of input signals and under 50ns in the acquisition time. This circuit will be able to be used in develops of high-performance microprocessors and digital systems.