• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2002.11a
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• pp.318.1-318
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• 2002

In this paper, the results of an analysis of the dynamic behavior of the eddy current brake(ECB) system are presented. The measured irregularity of the track in Korean high speed line and the track irregularity given by ERRI(high level) were used for simulation. The wheel-rail profile combination were analyzed with different rail gauges. A model of the bogie with an substitute body fur the carbody was implemented in the Multi-Body-Simulation Program Simpack. (omitted)

• Proceedings of the KIPE Conference
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• 2004.11a
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• pp.90-95
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• 2004

본 연구에서는 일반적으로 사용되고 있는 랜덤 수 발생 알고리즘인 LCG(Linear Congruential Generator)대신에 카오스 2중 텐트사상(Tent Mapping)에 의한 저 스위칭 소음 유도모터구동 시스템을 제안하였다. 2중 텐트사상에 의한 랜덤 수 발생을 위해 카오스 발생 영역인 $\lambda=0.99$에서의 2중 텐트사상의 분기도(Bifurcation Diagram)를 사용하였다. 카오스 랜덤수와 3상 기준 정현파는 80C196 마이크로 콘트롤러가 전담하고 있으며, 80C196으로부터 발생된 카오스 랜덤 수에 의하여 MAX038로부터 랜덤 주파수의 삼각파 캐리어가 발생된다. 기계적인 소음이 없는 ECB(Eddy current Brake)를 부하로 사용한 3상 유도모터 구동 장치를 제작하여 본 연구의 타당성을 입증하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.151-153
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• 2016

80/128-비트 마스터키 길이와 ECB, CBC, OFB, CTR의 4가지 운영모드를 지원하는 PRESENT 경량 블록암호 프로세서를 설계하고, Virtex5 FPGA에 구현하여 정상 동작함을 확인하였다. PRESENT 크립토 프로세서를 $0.18{\mu}m$ 공정의 CMOS 셀 라이브러리로 합성한 결과 8,237 GE로 구현되었으며, 최대 434 MHz 클록으로 동작하여 868 Mbps의 성능을 갖는 것으로 예측되었다.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.710-712
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• 2007

The effects of stress on the IZO/PC substrate and the electro-optical properties of a flexible LCD with microstructure in bending were investigated. It showed that the IZO/PC substrate and the periodic cross spacers are good enough to be employed in the application of the ECB or polarization rotation LC mode.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.11
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• pp.2093-2099
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• 2016

This paper describes a design of crypto-processor that supports multiple block cipher algorithms of PRESENT, ARIA, and AES. The crypto-processor integrates three cores that are PRmo (PRESENT with mode of operation), AR_AS (ARIA_AES), and AES-16b. The PRmo core implementing 64-bit block cipher PRESENT supports key length 80-bit and 128-bit, and four modes of operation including ECB, CBC, OFB, and CTR. The AR_AS core supporting key length 128-bit and 256-bit integrates two 128-bit block ciphers ARIA and AES into a single data-path by utilizing resource sharing technique. The AES-16b core supporting key length 128-bit implements AES with a reduced data-path of 16-bit for minimizing hardware. Each crypto-core contains its own on-the-fly key scheduler, and consecutive blocks of plaintext/ciphertext can be processed without reloading key. The crypto-processor was verified by FPGA implementation. The crypto-processor implemented with a $0.18{\mu}m$ CMOS cell library occupies 54,500 gate equivalents (GEs), and it can operate with 55 MHz clock frequency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.4
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• pp.795-803
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• 2017

This paper describes a dual-standard cryptographic processor that efficiently integrates two block ciphers ARIA and AES into a unified hardware. The ARIA-AES crypto-processor was designed to support 128-b and 256-b key sizes, as well as four modes of operation including ECB, CBC, OFB, and CTR. Based on the common characteristics of ARIA and AES algorithms, our design was optimized by sharing hardware resources in substitution layer and in diffusion layer. It has on-the-fly key scheduler to process consecutive blocks of plaintext/ciphertext without reloading key. The ARIA-AES crypto-processor that was implemented with a $0.18{\mu}m$ CMOS cell library occupies 54,658 gate equivalents (GEs), and it can operate up to 95 MHz clock frequency. The estimated throughputs at 80 MHz clock frequency are 787 Mbps, 602 Mbps for ARIA with key size of 128-b, 256-b, respectively. In AES mode, it has throughputs of 930 Mbps, 682 Mbps for key size of 128-b, 256-b, respectively. The dual-standard crypto-processor was verified by FPGA implementation using Virtex5 device.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.7
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• pp.1296-1302
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• 2016

A hardware implementation of ultra-lightweight block cipher algorithm PRESENT that was specified as a block cipher standard for lightweight cryptography ISO/IEC 29192-2 is described in this paper. Two types of crypto-core that support master key size of 80-bit are designed, one is for encryption-only function, and the other is for encryption and decryption functions. The designed PR80 crypto-cores implement the basic cipher mode of operation ECB (electronic code book), and it can process consecutive blocks of plaintext/ciphertext without reloading master key. The PR80 crypto-cores were designed in soft IP with Verilog HDL, and they were verified using Virtex5 FPGA device. The synthesis results using $0.18{\mu}m$ CMOS cell library show that the encryption-only core has 2,990 GE and the encryption/decryption core has 3,687 GE, so they are very suitable for IoT security applications requiring small gate count. The estimated maximum clock frequency is 500 MHz for the encryption-only core and 444 MHz for the encryption/decryption core.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11C
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• pp.1077-1087
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• 2003

In this paper, we proposed an architecture of a cryptosystem with various operating modes for the network security and implemented in hardware using the ASIC library. For configuring a cryptosystem, the standard block ciphers such as AES, SEED and 3DES were included. And the implemented cryptosystem can encrypt and decrypt the data in real time through the wired/wireless network with the minimum latency time (minimum 64 clocks, maximum 256 clocks). It can support CTR mode which is widely used recently as well as the conventional block cipher modes such as ECB, CBC and OFB, and operates in the multi-bit mode (64, 128, 192, and 256 bits). The implemented hardware has the expansion possibility for the other algorithms according to the network security protocol such as IPsec and the included ciphering blocks can be operated simultaneously. The self-ciphering mode and various ciphering mode can be supported by the hardware sharing and the programmable data-path. The global operation is programmed by the serial communication port and the operation is decided by the control signals decoded from the instruction by the host. The designed hardware using VHDL was synthesized with Hynix 0.25$\mu\textrm{m}$ CMOS technology and it used the about 100,000 gates. Also we could assure the stable operation in the timing simulation over 100㎒ using NC-verilog.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.7 s.361
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• pp.71-80
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• 2007

This paper describes an efficient hardware design of WiBro security processor (WBSec) supporting for the security sub-layer of WiBro wireless internet system. The WBSec processor, which is based on AES (Advanced Encryption Standard) block cipher algorithm, performs data oncryption/decryption, authentication/integrity, and key encryption/decryption for packet data protection of wireless network. It carries out the modes of ECB, CTR, CBC, CCM and key wrap/unwrap with two AES cores working in parallel. In order to achieve an area-efficient implementation, two design techniques are considered; First, round transformation block within AES core is designed using a shared structure for encryption/decryption. Secondly, SubByte/InvSubByte blocks that require the largest hardware in AES core are implemented using field transformation technique. It results that the gate count of WBSec is reduced by about 25% compared with conventional LUT (Look-Up Table)-based design. The WBSec processor designed in Verilog-HDL has about 22,350 gates, and the estimated throughput is about 16-Mbps at key wrap mode and maximum 213-Mbps at CCM mode, thus it can be used for hardware design of WiBro security system.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.27 no.9
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• pp.1492-1498
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• 2003

This study proposes a new conceptual Hybrid Electric Brake System (HEBS) which overcomes problems of a conventional hydraulic brake system. HEBS adopt a contactless type bake system when a vehicle speed is high, to obtain superior braking performances by eddy current. On the contrary, when a vehicle speed is low, HEBS employs a contact type brake system such as conventional hydraulic brake system to generate higher brake force. Therefore, HEBS transfers faster the braking intention of drivers and guarantees the safety of drivers. Braking torque analysis is performed by using a mathematical model which is proposed to investigate the characteristic of a vehicle dynamics when the brake torque is applied. Optimal torque control is achieved by maintaining a desired slip corresponding to the road condition. The results show that HEBS reduces the stopping distance, saves the electric energy, and increases the stability.