• Journal of IKEEE
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• v.17 no.2
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• pp.202-207
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• 2013

This paper implemented the conventional FAST and BRIEF algorithm as hardware on Zynq-7000 SoC Platform. Previous feature-based hardware accelerator is mostly implemented using the SIFT or SURF algorithm, but it requires excessive internal memory and hardware cost. The proposed FAST & BRIEF accelerator reduces approximately 57% of internal memory usage and 70% of hardware cost compared to the conventional SIFT or SURF accelerator, and it processes 0.17 pixel per Clock.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.7
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• pp.1071-1077
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• 2022

A security SoC that can be used to implement elliptic curve cryptography (ECC) based public-key infrastructures was designed. The security SoC has an architecture in which a hardware accelerator for the elliptic curve digital signature algorithm (ECDSA) is interfaced with the Cortex-A53 CPU using the AXI4-Lite bus. The ECDSA hardware accelerator, which consists of a high-performance ECC processor, a SHA3 hash core, a true random number generator (TRNG), a modular multiplier, BRAM, and control FSM, was designed to perform the high-performance computation of ECDSA signature generation and signature verification with minimal CPU control. The security SoC was implemented in the Zynq UltraScale+ MPSoC device to perform hardware-software co-verification, and it was evaluated that the ECDSA signature generation or signature verification can be achieved about 1,000 times per second at a clock frequency of 150 MHz. The ECDSA hardware accelerator was implemented using hardware resources of 74,630 LUTs, 23,356 flip-flops, 32kb BRAM, and 36 DSP blocks.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.1
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• pp.21-31
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• 2017

In this paper, the Zynq system-on-chip (SoC) platform is used to design an adaptive noise reduction and edge-detection system using partial reconfiguration. Filters are implemented in a partially reconfigurable (PR) region to provide high computational complexity in real-time, 1080p video processing. In addition, partial reconfiguration enables better utilization of hardware resources in the embedded system from autonomous replacement of filters in the same PR region. The proposed edge-detection system performs adaptive noise reduction if the noise density level in the incoming video sequences exceeds a given threshold value. Results of implementation show that the proposed system improves the accuracy of edge-detection results (14~20 times in Pratt's Figure of Merit) through self-reconfiguration of filter bitstreams triggered by noise density level in the video sequences. In addition, the ZyCAP controller implemented in this paper enables about 2.1 times faster reconfiguration when compared to a PCAP controller.

• Journal of information and communication convergence engineering
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• v.13 no.3
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• pp.145-151
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• 2015

We describe in this paper a hardware-based improvement scheme of a real-time automatic speech recognition (ASR) system with respect to speed by designing a parallel feature extraction algorithm on a Field-Programmable Gate Array (FPGA). A computationally intensive block in the algorithm is identified implemented in hardware logic on the FPGA. One such block is mel-frequency cepstrum coefficient (MFCC) algorithm used for feature extraction process. We demonstrate that the FPGA platform may perform efficient feature extraction computation in the speech recognition system as compared to the generalpurpose CPU including the ARM processor. The Xilinx Zynq-7000 System on Chip (SoC) platform is used for the MFCC implementation. From this implementation described in this paper, we confirmed that the FPGA platform is approximately 500× faster than a sequential CPU implementation and 60× faster than a sequential ARM implementation. We thus verified that a parallelized and optimized MFCC architecture on the FPGA platform may significantly improve the execution time of an ASR system, compared to the CPU and ARM platforms.

• Nuclear Engineering and Technology
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• v.54 no.6
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• pp.2023-2030
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• 2022

A novel pulse fitting analysis (PFA) method is presented for the acquisition of nuclear spectra. The charging process of the feedback capacitor in the resistive feedback charge-sensitive preamplifier is equivalent to the impulsive pulse, and its impulse response function (IRF) can be obtained by non-linear fitting of the falling edge of the nuclear pulse. The integral of the IRF excluding the baseline represents the energy deposition of the particles in the detector. In addition, since the non-linear fitting process in PFA method is difficult to achieve in the conventional architecture of spectroscopy system, a new multi-channel analyzer (MCA) based on Zynq SoC is proposed, which transmits all the data of nuclear pulses from the programmable logic (PL) to the processing system (PS) by high-speed AXI-Stream in order to implement PFA method with precision. The linearity of new MCA has been tested. The spectrum of ¹³⁷Cs was obtained using LaBr₃(Ce) scintillator detector, and was compared with commercial MCA by ORTEC. The results of tests indicate that the MCA based on PFA method has the same performance as the commercial MCA based on pulse height analysis (PHA) method and excellent linearity for γ-rays with different energies, which infers that PFA method is an effective and promising method for the acquisition of spectra. Furthermore, it provides a new solution for nuclear pulse processing algorithms involving regression and iterative processes.