• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.9
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• pp.1803-1810
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• 2009

This paper designed IQ imbalance estimator and compensator to cancel the IQ imbalance error in DVB-T system using OFDM by Matlab. Among Matlab model, we designed and implemented IQ imbalance estimator and compensator by System Generator of Xilinx and Matlab model compared with Xilinx System Generator Model for FPGA implementation. As a result of simulation, we confirmed that both model estimated and compensated IQ imbalance error very well. Also, we verified the performance through hardware co-simulation, timing analysis and resource estimation with Xilinx Spartan3 xc3s1000 fg676-4 target Device.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.5
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• pp.906-911
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• 2008

This paper designed Simulik Model to cancel the carrier frequency offset in OFDM using CORDIC Algorithm and evaluated its performance. And Simulink Model compared with Xilinx System Generator Model for FPGA implementation. As a result of simulation, we confirmed that both model is error free by CORDIC when offset frequency is lower than $10^5MHz$. Also, we verified the performance through Hardware Co-simulation with Xilinx Spartan3 xc3s1000 fg676-4 Target Device, and timing analysis and resource estimation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.06a
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• pp.179-183
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• 2007

This paper is to implement a low power frequency Shift Keying(FSK) receiver using Xilinx System Generator. The receiver incorporates a 16 point Fast Fourier Transform(FFT) for symbol detection. The design units of the receiver are digital designs for better efficiency and reliability. The receiver functions on one bit data processing and supports data rates 10kbps. In addition CORDIC algorithm is used for avoiding complex multiplications while computing FFT, multiplication of twiddle factor is substituted by rotators. The design and simulation of the receiver is carried out in Simulink, then the simulink model is translated to a hardware model to implement FPGA using Xilinx System Generator and to verify performance.

• Proceedings of the KAIS Fall Conference
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• 2003.06a
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• pp.250-252
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• 2003

본 논문에서는 콘벌루션 부호를 사용한 대역확산 방식의 디지틀 통신모뎀을 FPGA를 이용하여 설계 및 검증을 하였다. 대역확산 방식에서의 콘벌루tus부호기(K=3, R=1/2), PN code(128chip) generator와 비터비 디코더를 Xilinx사의 FPGA 디자인 툴인 Xilinx Foundations3.1을 사용하여 VHDL simulation과 timing simulation을 수행하였고, FPGA 회로설계 검증 장비인 EDA-Lab 3000 장비를 사용하여 Xilinx사의 SPARTAN2 2S100PQ208칩에 configuration 한 후 Agilent사의 1681A logic analyzer를 사용하여 설계된 회로의 동작을 검증하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.8
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• pp.1488-1494
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• 2008

This paper is to design and implement a low power noncoherent BFSK receiver intended for future deep space communication using Xilinx System generator. The receiver incorporates a 16 point Fast Fourier Transform(FFT) for symbol detection. The design units of the receiver are digital design for better efficiency and reliability. The receiver functions on one bit data processing and supports main data rate 10kbps. In addition CORDIC algorithm is used for avoiding complex multiplications while computing FFT and multiplication of twiddle factor for low power is substituted by rotators. The design and simulation of the receiver is carried out in Simulink then the Simulink model is translated to the hardware model to implement FPGA using Xilinx System Generator and to verify performance.

• Journal of international Conference on Electrical Machines and Systems
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• v.3 no.2
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• pp.110-115
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• 2014

The reconfigurability of FPGA devices allows designers to evaluate, test and validate a new control algorithm; a new component or prototypes without damaged the real system with the so-called hardware co-simulation. The present paper uses the Xilinx System Generator (XSG) environment to establish and validate a new nonlinear estimator for the rotor time constant inverse that will be exploited to improve the indirect rotor field control of induction motor.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.907-910
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• 2009

This paper is the FPGA Implementation of Reed-Solomon Encoder that is one of Error control Codes. Reed-Solomon codes are block-based error control codes with a wide range of applications in digital communications. RS codes are strong on burst errors because it process signals as symbol. We simulate this system using Matlab from Mathworks and design it using System Generator from Xilinx. We refer Matlab source in Implementation of Reed-Solomon Error Control Coding for Compressed Images by Simon Anthony Raspa.

• Journal of Information Processing Systems
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• v.9 no.3
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• pp.499-510
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• 2013

Hardware-Software co-simulation of a multiple image encryption technique shall be described in this paper. Our proposed multiple image encryption technique is based on the Latin Square Image Cipher (LSIC). First, a carrier image that is based on the Latin Square is generated by using 256-bits of length key. The XOR operation is applied between an input image and the Latin Square Image to generate an encrypted image. Then, the XOR operation is applied between the encrypted image and the second input image to encrypt the second image. This process is continues until the nth input image is encrypted. We achieved hardware co-simulation of the proposed multiple image encryption technique by using the Xilinx System Generator (XSG). This encryption technique is modeled using Simulink and XSG Block set and synthesized onto Virtex 2 pro FPGA device. We validated our proposed technique by using the hardware software co-simulation method.

• Journal of the Institute of Convergence Signal Processing
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• v.14 no.1
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• pp.39-44
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• 2013

In this paper digital phase-shifter for multi-arm spiral antennas was designed by using Hilbert transform. All frequency components in input signal are phase-shifted for 90 degree by Hilbert transform, and the transform is implemented by FIT and IFIT. Digital phase-shifter generates two signals with phase difference of 90 degree by using Hilbert transform from input signals sampled by analog-digital converter(ADC), and then the input signal is phase-shifted for a given phase by using two signals. Hilbert transform based on digital phase-shifter is designed by Xilinx System generator, and the effects of input noise, FIT point, sampling period, initial phase of input signal, and shifted phase are simulated and its results are compared with Matlab results.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.621-622
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• 2017

In this paper, a low-complexity FFT processor is proposed for narrow-band interference signal cancellation based array antenna. The proposed FFT pocessor can support the variable length of 64, 128 and 512. By reducing number of non-tirval multipliers with mixed radix-4/2/4/2/4/2 algorithm and flexible multi-path delay commutator(MDC) architecture, the complexity of the proposed FFT processor is dramatically decreased. The proposed FFT processor was designed in Xilinx system generator and Implemented with Xilinx Virtex-7 FPGA. With the proposed architecture, the number of slices for the processor is 11454, and the number of DSP48s is 194.