• Progress in Superconductivity
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• 제7권2호
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• pp.109-113
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• 2006

The Arithmetic Logic Unit (ALU) is a core element of a computer processor that performs arithmetic and logic operations on the operands in computer instruction words. We have developed and tested an RSFQ multi-bit ALU constructed with half adder unit cells. To reduce the complexity of the ALU, We used half adder unit cells. The unit cells were constructed of one half adder and three de switches. The timing problem in the complex circuits has been a very important issue. We have calculated the delay time of all components in the circuit by using Josephson circuit simulation tools of XIC, $WRspice^{TM}$, and Julia. To make the circuit work faster, we used a forward clocking scheme. This required a careful design of timing between clock and data pulses in ALU. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. The fabricated 1-bit, 2-bit, and 4-bit ALU circuits were tested at a few kilo-hertz clock frequency as well as a few tens giga-hertz clock frequency, respectively. For high-speed tests, we used an eye-diagram technique. Our 4-bit ALU operated correctly at up to 5 GHz clock frequency.

• 한국ITS학회 논문지
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• 제1권1호
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• pp.10-16
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• 2002

본 논문은 논리연산을 이용한 주행차량들의 영상분할 알고리즘을 제안하였다. 연속된 프레임 간에 XOR(Exclusive OR)연산을 행함으로써 차영상을 구하였고, Laplacian 필터링, AND 연산, 팽창(dilation)연산 등을 이용하여 주행차량들에 대해서만 에지들을 추출하고 이들을 영상분할 함으로써 기존방법에 비해 평활화 단계에서 나타날 수 있는 잡음을 제거하였고, 전처리 단계를 줄였으며, 알고리즘을 단순화 하였다 또한 분할된 영상으로부터 컬러 등 주행차량의 특징을 직접 추출 가능토록 하였다. 30fps로 90,000프레임 이상 촬영 된 주행차량들을 대상으로 제안된 알고리즘의 우수성을 보였다

• 공학논문집
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• 제2권1호
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• pp.31-37
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• 1997

본 논문에서의 ALU는 덧셈, 뺄셈, 1증가, 1 감소, 2의 보수 등의 산술 연산을 수행하는 산술 연산 회로, 논리합, 논리곱, 배타논리합, 부정과 같은 논리 연산을 수행하는 논리 연산 회로, 쉬프트 연산 및 산술 혹은 논리 연산 회로의 연산 결과를 데이터 버스로 전송하는 기능을 담당하는 쉬프터로 구성되며, 이러한 기본적인 ALU 기능과 관련된 명령어는 Z80 명령어에서 추출하여 ALU의 내부 회로를 설계하였고, 이 설계된 회로를 그래픽 화면으로 구성하여 데이터의 연산이 ALU 내부에서 어떤 과정과 경로를 거쳐 수행되는 가를 비트 및 논리 게이트 단위까지 처리하여 ALU 구조와 단계별 연산 과정을 그래픽 형태로 학습하는 교육 시스템이다.

• 대한전자공학회논문지SD
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• 제46권12호
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• pp.1-9
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• 2009

가산기는 기본적인 산술 연간 장치로써, 산술 연산 시스템 전체의 속도 및 전력소모에 결정적인 역할을 한다. 단일 비트 전가산기의 성능을 향상시키는 문제는 시스템 성능 향상의 기본적인 요소이다. 주 논문에서는 기존의 모듈 I과 모듈III를 거쳐 출력 Cout을 갖는 XOR-XNOR 구조와는 달리 모듈 I을 거치지 않고 입력 A, B, Cin에 의해 모듈III를 거쳐 출력 Cout을 갖는 새로운 구조를 이용한다. 최대 5단계의 지연단계를 2단계로 줄인 전가산기를 제안한다. 따라서 Cout 출력속도가 향상되어 리플캐리 가산기와 같은 직렬연결의 경우 더욱 좋은 성능을 나타내고 있다. 제안한 1Bit 전가산기는 static CMOS, CPL, TFA, HPSC, TSAC 전가산기에 비해 좋은 성능을 가지고 있다. 가장 좋은 성능을 나타내는 기존의 전가산기에 비해 4.3% 향상된 지연시간을 가지며 9.8%의 향상된 PDP 비율을 갖는다. 제안한 전가산기 회로는 HSPICE 툴을 이용하여 $0.18{\mu}m$ CMOS 공정에서 전력소모 및 동작속도를 측정하였으며 공급전압에 따른 특성을 비교하였다.

• 한국초전도ㆍ저온공학회논문지
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• 제7권1호
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• pp.9-12
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• 2005

We have constructed an RSFQ 4-bit Arithmetic Logic Unit (ALU) in a pipelined structure. An ALU is a core element of a computer processor that performs arithmetic and logic operation on the operands in computer instruction words. We have simulated the circuit by using Josephson circuit simulation tools. We used simulation tools of XIC, $WRspice^{TM}$, and Julia. To make the circuit work faster, we used a forward clocking scheme. This required a careful design of timing between clock and data pulses in ALU. The RSFQ 1-bit block of ALU used in constructing the 4-bit ALU was consisted of three DC current driven SFQ switches and a half-adder. By commutating output ports of the half adder, we could produce AND, OR, XOR, or ADD functions. The circuit size of the 4-bit ALU when fabricated was 3 mm x 1.5 mm, fitting in a 5 mm x 5mm chip. The fabricated 4-bit ALU operated correctly at 5 GHz clock frequency. The chip was tested at the liquid-helium temperature.

• Journal of the Optical Society of Korea
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• 제19권6호
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• pp.592-603
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• 2015

In this paper, an optical implementation of a novel asymmetrical cryptosystem combined with D-H secret key sharing and triple DES is proposed. The proposed optical cryptosystem is realized by performing free-space interconnected optical logic operations such as AND, OR and XOR which are implemented in Mach-Zehnder type interferometer architecture. The advantage of the proposed optical architecture provides dual outputs simultaneously, and the encryption optical setup can be used as decryption optical setup only by changing the inputs of SLMs. The proposed cryptosystem can provide higher security strength than the conventional electronic algorithm, because the proposed method uses 2-D array data, which can increase the key length surprisingly and uses 3DES algorithm, which protects against “meet in the middle” attacks. Another advantage of the proposed asymmetrical cryptosystem is that it is free to change the user’s two private random numbers in generating the public keys at any time. Numerical simulation and performance analysis verify that the proposed asymmetric cryptosystem is effective and robust against attacks for the asymmetrical cipher system.

• 한국초전도저온공학회:학술대회논문집
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• 한국초전도저온공학회 2003년도 추계학술대회 논문집
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• pp.117-119
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• 2003

We have designed fabricated, and tested an RSFQ(Rapid Single Flux Quantum) 1-bit ALU (Arithmetic Logic Unit). The 1-bit ALU was composed of a half adder and three SFQ DC switches. Three DC switches were attached to the two output ports of an ALU for the selection of each function from the available functions that were AND, OR, XOR and ADD. And we also attached two DC switches at the input ports of the half adder so that the input data were controlled using the function generators operating at low speed while we tested the circuit at high speed. The test bandwidth was from 1KHz to 5 ㎓. The chip was tested at the liquid helium temperature of 4.2 K.

• 한국정보전자통신기술학회논문지
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• 제12권6호
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• pp.567-572
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• 2019

본 논문에서는 이진영상과 이진커널을 사용하여 컨볼루션, 풀링, ReLU 연산을 수행하는 이진 CNN 연산 알고리즘을 제안한다. 256 그레이스케일 영상을 8개의 비트평면으로 분해하고, -1과 1로 구성되는 이진커널을 사용하는 방법이다. 이진영상과 이진커널의 컨볼루션 연산은 가산과 감산으로 수행한다. 논리적으로는 XNOR 연산과 비교기로 구성되는 이진연산 알고리즘이다. ReLU와 풀링 연산은 각각 XNOR와 OR 논리연산으로 수행한다. 본 논문에서 제안한 알고리즘의 유용성을 증명하기 위한 실험을 통해, CNN 연산을 이진 논리연산으로 변환하여 수행할 수 있음을 확인한다. 이진 CNN 알고리즘은 컴퓨팅 파워가 약한 시스템에서도 딥러닝을 구현할 수 있는 알고리즘으로 스마트 폰, 지능형 CCTV, IoT 시스템, 자율주행 자동차 등의 임베디드 시스템에서 다양하게 적용될 수 있는 시스템이다.

• ETRI Journal
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• 제35권3호
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• pp.448-458
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• 2013

This paper presents a generalized post-processing technique for enhancing the pseudorandomness of digital chaotic oscillators through a nonlinear XOR-based operation with rotation and feedback. The technique allows full utilization of the chaotic output as pseudorandom number generators and improves throughput without a significant area penalty. Digital design of a third-order chaotic system with maximum function nonlinearity is presented with verified chaotic dynamics. The proposed post-processing technique eliminates statistical degradation in all output bits, thus maximizing throughput compared to other processing techniques. Furthermore, the technique is applied to several fully digital chaotic oscillators with performance surpassing previously reported systems in the literature. The enhancement in the randomness is further examined in a simple image encryption application resulting in a better security performance. The system is verified through experiment on a Xilinx Virtex 4 FPGA with throughput up to 15.44 Gbit/s and logic utilization less than 0.84% for 32-bit implementations.

• Journal of Electrical Engineering and Technology
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• 제3권1호
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• pp.43-51
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• 2008

Evolutionary Algorithms (EAs) cover all the applications involving the use of Evolutionary Computation in electronic system design. It is largely applied to complex optimization problems. EAs introduce a new idea for automatic design of electronic systems; instead of imagine model, ions, and conventional techniques, it uses search algorithm to design a circuit. In this paper, a method for automatic optimization of the digital circuit design method has been introduced. This method is based on randomized search techniques mimicking natural genetic evolution. The proposed method is an iterative procedure that consists of a constant-size population of individuals, each one encoding a possible solution in a given problem space. The structure of the circuit is encoded into a one-dimensional genotype as represented by a finite string of bits. A number of bit strings is used to represent the wires connection between the level and 7 types of possible logic gates; XOR, XNOR, NAND, NOR, AND, OR, NOT 1, and NOT 2. The structure of gates are arranged in an $m{\times}n$ matrix form in which m is the number of input variables.