• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.8
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• pp.136-142
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• 2013

CRC features have been added to increase the reliability of the data in memory products for high-speed operation, such as DDR4. High-speed memory products in a shortage of internal timing margin increases for the CRC calculation. Because the existing CRC requires many additional circuit area and delay time. In this paper, we show that the matrix-type CRC and a new XOR/XNOR gate could be improved the circuit area and delay time. Proposed matrix-type CRC can detect all odd-bit errors and can detect even number of bit errors, except for multiples of four bits. In addition, a single error in the error correction can reduce the burden of re-transmission of data between memory products and systems due to CRC errors. In addition, the additional circuit area, compared to existing methods can be improved by 57%. The proposed XOR gate which is consists of six transistors, it can reduce the area overhead of 35% compared to the existing CRC, 50% of the gate delay can be reduced.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.1
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• pp.46-56
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• 2017

Recently, the spread of IoT technology has been spreading, and it has been applied to all industrial fields such as home / home appliance / medical care. Due to the low specification, low power consumption characteristic and communication data characteristic of IoT, implementation of existing algorithm is difficult thing. From this reason, we have proposed for the first time that encryption and decryption can be proceeded by introducing a kind of variable length bit XOR operation method which changes a variable the bit length value by using carry up and carry down method. We confirmed the practicality of encrypting short message data frequently processed by IoT device / QR code / RFID / NFC without changing the size of data before and after encryption.

• Journal of the Korea Society of Computer and Information
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• v.19 no.10
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• pp.81-89
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• 2014

In this paper, we propose SA hash algorithm to avoid upload identical files and design server system using proposed SA hash algorithm. Client to want to upload file examines the value of SA hash and if the same file is found in server system client use the existing file without upload. SA hash algorithm which is able to examine the identical-file divides original file into blocks of n bits. Original file's mod i bit and output hash value's i bit is calculated with XOR operation. It is SA hash algorithm's main routine to repeat the calculation with XOR until the end of original file. Using SA hash algorithm which is more efficient than MD5, SHA-1 and SHA-2, we can design server system to avoid uploading identical file and save storage capacity and upload-time of server system.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.156-163
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• 2012

Recently, Information Hiding Technology are becoming increasingly demanding in the field of international security, military and medical image This paper proposes data hiding technique utilizing parity checker for gray level image. many researches have been adopted LSB substitution and XOR operation in the field of steganography for the low complexity, high embedding capacity and high image quality. But, LSB substitution methods are not secure through it's naive mechanism even though it achieves high embedding capacity. Proposed method replaces LSB of each pixel with XOR(between the parity check bit of other 7 MSBs and 1 Secret bit) within one pixel. As a result, stego-image(that is, steganogram) doesn't result in high image degradation. Eavesdropper couldn't easily detect the message embedding. This approach is applying the concept of symmetric-key encryption protocol onto steganography. Furthermore, 1bit of symmetric-key is generated by the self-reference of each pixel. Proposed method provide more 25% embedding rate against existing XOR operation-based methods and show the effect of the reversal rate of LSB about 2% improvement.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.41-50
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• 2005

As the size of circuits becomes larger, the test method needs more test data volume and larger test application time. In order to reduce test data volume and test application time, a new test data compression/decompression method is proposed. The proposed method is based on an XOR network uses don't-care-bits to improve compression ratio during seed vectors generation. After seed vectors are produced seed vectors can be merged using two prefix codes. It only requires 1 clock time for reusing merged seed vectors, so test application time can be reduced tremendously. Experimental results on large ISCAS '89 benchmark circuits prove the efficiency of the proposed method.

• Journal of Broadcast Engineering
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• v.16 no.2
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• pp.274-292
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• 2011

This paper proposes an efficient coding method of the depth-map which is different from the natural images. The depth-map are so smooth in both inner parts of the objects and background, but it has sharp edges on the object-boundaries like a cliff. In addition, when a depth-map block is decomposed into bit planes, the characteristic of perfect matching or inverted matching between bit planes often occurs on the object-boundaries. Therefore, the proposed depth-map coding scheme is designed to have the bit-plane unit coding method using the adaptive XOR method for efficiently coding the depth-map images on the object-boundary areas, as well as the conventional DCT-based coding scheme (for example, H.264/AVC) for efficiently coding the inside area images of the objects or the background depth-map images. The experimental results show that the proposed algorithm improves the average bit-rate savings as 11.8 % ~ 20.8% and the average PSNR (Peak Signal-to-Noise Ratio) gains as 0.9 dB ~ 1.5 dB in comparison with the H.264/AVC coding scheme. And the proposed algorithm improves the average bit-rate savings as 7.7 % ~ 12.2 % and the average PSNR gains as 0.5 dB ~ 0.8 dB in comparison with the adaptive block-based depth-map coding scheme. It can be confirmed that the proposed method improves the subjective quality of synthesized image using the decoded depth-map in comparison with the H.264/AVC coding scheme. And the subjective quality of the proposed method was similar to the subjective quality of the adaptive block-based depth-map coding scheme.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.38-47
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• 1999

We have designed a 16bit adder which reduces the power consumption at each level of architecture, logic and transistor. The conventional ELM adder has a major disadvantage which makes glitch in the G cell when the particular input bit patterns are applied, because of the block carry generation signal computed by the input bit pattern. Thus, we propose a low power adder architecture which can automatically transfer each block carry generation signal to the G cell of the last level to avoid glitches for particular input bit patterns at the architecture level. We also use a combination of logic styles which is suitable for low power consumption with static CMOS and low power XOR gate at the logic level. Futhermore, The variable-sized cells are used for reduction of power consumption according to the logic depth of the bit propagation at the transistor level. As a result of HSPICE simulation with $0.6\mu\textrm{m}$ single-poly triple-metal LG CMOS standard process parameter, the proposed adder is superior to the conventional ELM architecture with fixed-sized cell and fully static CMOS by 23.6% in power consumption, 22.6% in power-delay-product, respectively.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.5
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• pp.87-93
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• 2002

SHACAL is based on the hash standard SHA-1 used in encryption mode, as a submission to NESSIE. SHACAL uses the XOR, modular addition operation and the functions of bit-by-bit manner. These operations and functions make the differential cryptanalysis difficult, i.e, we hardly find a long differential with high probability. But, we can find short differentials with high probability. Using this fact, we discuss the security of SHACAL against the amplified boomerang attack. We find a 36-step boomerang-distinguisher and present attacks on reduced-round SHACAL with various key sizes. We can attack 39-step with 256-bit key, and 47-step with 512-bit key.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.8 s.338
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• pp.11-16
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• 2005

This paper proposes a bit manipulation accelerator (BMA) having application specific instructions, which efficiently supports scrambling, convolutional encoding, puncturing, and interleaving. Conventional DSPs cannot effectively perform bit manipulation functions since かey have multiply accumulate (MAC) oriented data paths and word-based functions. However, the proposed accelerator can efficiently process bit manipulation functions using parallel shift and Exclusive-OR (XOR) operations and bit jnsertion/extraction operations on multiple data. The proposed BMA has been modeled by VHDL and synthesized using the SEC $0.18\mu m$ standard cell library and the gate count of the BMA is only about 1,700 gates. Performance comparisons show that the number of clock cycles can be reduced about $40\%\sim80\%$ for scrambling, convolutional encoding and interleaving compared with existing DSPs.

• Journal of IKEEE
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• v.18 no.4
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• pp.509-516
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• 2014

CRC feature in a high-speed semiconductor memory devices such as DDR4/GDDR5 increases the data reliability. Conventional CRC method have a massive area overhead and long delay time. It leads to insufficient internal timing margins for CRC calculation. This paper, presents a CRC code method that provides error detection and a real-time matrix type CRC. If there are errors in the data, proposed method can alert to the system in a real-time manner. Compare to the conventional method(XOR 6 stage ATM-8 HEC code), the proposing method can improve the error detection circuits up to 60% and XOR stage delay by 33%. Also the real-time error detection scheme can improve the error detection speed to agerage 50% for the entire data bits(UI0~UI9).