• Journal of the Korea Society of Computer and Information
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• v.7 no.4
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• pp.89-93
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• 2002

This paper describes an ALU core which is suitable for 32-bit DSP This ALU operates in 32-bit data and occupies the third stage, execution, among 5 stage pipeline structure. The supplied functions of the ALU are arithmetic operations, logical operations, shifting, and so on. For the implementation of this ALU core, each functional block is described by HDL. And the functional verification of the ALU core is performed through HDL simulation. This ALU is designed to use the 32-bit DSP.

• Proceedings of the Korea Information Processing Society Conference
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• 2019.10a
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• pp.449-452
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• 2019

초 경량암호 CHAM은 자원이 제한된 장치 상에서 효율성이 뛰어난 덧셈, 회전연산, 그리고 XOR 연산으로 이루어진 알고리즘이다. CHAM은 특히 사물인터넷 플랫폼에서 높은 연산 성능을 보인다. 하지만 사물 인터넷 상에서 사용되는 경량 블록 암호화 알고리즘은 부채널 분석에 취약할 수 있다. 본 논문에서는 CHAM에 대한 1차 전력 분석 공격을 시도하여 부채널 공격에 대한 취약성을 증명한다. 이와 더불어 해당 공격을 안전하게 방어할 수 있도록 마스킹 기법을 적용하여 안전한 알고리즘을 제안한다.

• Journal of Korea Society of Industrial Information Systems
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• v.14 no.3
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• pp.15-21
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• 2009

In this paper, we proposed an iterative digital image watermarking technique using encrypted binary phase computer generated hologram in the discrete cosine transform(OCT) domain. For the embedding process of watermark, using simulated annealing algorithm, we would generate a binary phase computer generated hologram(BPCGH) which can reconstruct hidden image perfectly instead of hidden image and repeat the hologram and encrypt it through the XOR operation with key image that is ramdomly generated binary phase components. We multiply the encrypted watermark by the weight function and embed it into the DC coefficients in the DCT domain of host image and an inverse DCT is performed. For the extracting process of watermark, we compare the DC coefficients of watermarked image and original host image in the DCT domain and dividing it by the weight function and decrypt it using XOR operation with key image. And we recover the hidden image by inverse Fourier transforming the decrypted watermark. Finally, we compute the correlation between the original hidden image and recovered hidden image to determine if a watermark exits in the host image. The proposed watermarking technique use the hologram information of hidden image which consist of binary values and encryption technique so it is very secure and robust to the external attacks such as compression, noises and cropping. We confirmed the advantages of the proposed watermarking technique through the computer simulations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.6 s.336
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• pp.31-38
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• 2005

In this paper, we proposed an optical security system based on a gray-image exclusive-OR encryption using multi-phase separation and phase-wrapping method. For encryption, a gray image is sliced into binary images, which have the same pixel value, and these images are encrypted by modified XOR rules with binary random images. The XORed images and the binary images respectively combined and converted into full phase images, called an encrypted image and a key image. For decryption, when the encrypted image and key image are used as inputs on optical elements, Practically due to limited controllability of phase range in optical elements, the original gray image cannot be efficiently reconstructed by these optical elements. Therefore, by decreasing the phase ranges of the encrypted image and key image using a phase-wrapping method and separating these images into low-level phase images using multi-phase separation, the gray image can be reconstructed by optical elements which have limited control range. The decrytion process is simply implemented by interfering a multiplication result of encrypted image and key image with reference light. The validity of proposed scheme is verified and the effects, which are caused by phase limitation in decryption process, is analyzed by using computer simulations.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.6
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• pp.567-572
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• 2019

In this paper, we propose an algorithm to perform convolution, pooling, and ReLU operations in CNN using binary image and binary kernel. It decomposes 256 gray-scale images into 8 bit planes and uses a binary kernel consisting of -1 and 1. The convolution operation of binary image and binary kernel is performed by addition and subtraction. Logically, it is a binary operation algorithm using the XNOR and comparator. ReLU and pooling operations are performed by using XNOR and OR logic operations, respectively. Through the experiments to verify the usefulness of the proposed algorithm, We confirm that the CNN operation can be performed by converting it to binary logic operation. It is an algorithm that can implement deep running even in a system with weak computing power. It can be applied to a variety of embedded systems such as smart phones, intelligent CCTV, IoT system, and autonomous car.

• The Journal of Engineering Research
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• v.2 no.1
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• pp.31-37
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• 1997

This paper describes the design and implementation of 8 bit ALU graphic simulator which helps students who study the structure and operation course of general ALU. ALU of this paper consists of three parts, arithmetic circuit, logic circuit, and shifter. Each of them performs as follows. Arithmetic circuit performs arithmetic operation such as addition, subtraction, 1 increment, 1 decrement, 2's complement, logic circuit performs logic operation such as OR, AND, XOR, NOT, and shifter performs shift operation and transfers the result of circuits of arithmetic, logic to data bus. The instructions which relate to these basic ALU functions was selected from Z80 instructions and ALU circuit was designed with those instructions and this designed ALU circuit was implemented on graphic screen. And all state of this data operation course in ALU was showed by bit and logic gate unit.

• Proceedings of the Korean Information Science Society Conference
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• 2001.10a
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• pp.709-711
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• 2001

본 논문에서는 유한 확대 체 GF($^{m}$ )상에서 셀룰라 오토마타를 이용한 곱셈기 구조를 제안한다. 제안된 구조는 기약 다항식으로 AOP(All One Polynomial)의 특성을 사용하고 LSB방식으로 곱셈 연산을 수행한다. 제안된 곱셈기는 지연시간으로 m+1을 갖는 임계경로로는 1- $D_{AND}$+1- $D_{XOR}$를 갖는다. 특히 구조가 정규성, 모듈성, 병렬성을 가지기 때문에 VLSI구현에 효율적이다.적이다.

• Proceedings of the Korea Information Processing Society Conference
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• 2001.04a
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• pp.391-394
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• 2001

본 논문에서는 OFT(One-way Function Trees)를 사용한 안전한 멀티캐스트 프로토콜을 제안한다. 그룹 키의 생성시 모든 멤버의 참여를 보장하며, 각 멤버는 독립적으로 그룹키를 계산한다. 제안하는 프로토콜은 그룹키의 생성시 해쉬 함수와 비트단위 XOR 연산만을 수행하기 때문에 속도가 빠르며, 멤버의 가입, 탈퇴가 빈번히 발생하는 동적인 환경에서도 적합하다.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.43 no.5 s.311
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• pp.36-43
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• 2006

In this paper we present a new high-speed parallel multiplier for Performing the bit-parallel multiplication of two polynomials in the finite fields $GF(2^m)$. Prior to construct the multiplier circuits, we consist of the MOD operation part to generate the result of bit-parallel multiplication with one coefficient of a multiplicative polynomial after performing the parallel multiplication of a multiplicand polynomial with a irreducible polynomial. The basic cells of MOD operation part have two AND gates and two XOR gates. Using these MOD operation parts, we can obtain the multiplication results performing the bit-parallel multiplication of two polynomials. Extending this process, we show the design of the generalized circuits for degree m and a simple example of constructing the multiplier circuit over finite fields $GF(2^4)$. Also, the presented multiplier is simulated by PSpice. The multiplier presented in this paper use the MOD operation parts with the basic cells repeatedly, and is easy to extend the multiplication of two polynomials in the finite fields with very large degree m, and is suitable to VLSI. Also, since this circuit has a low propagation delay time generated by the gates during operating process because of not use the memory elements in the inside of multiplier circuit, this multiplier circuit realizes a high-speed operation.

• Proceedings of the Korean Information Science Society Conference
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• 2006.10c
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• pp.477-482
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• 2006

최근 Du 등은 공개키 암호 기반의 센서네트워크에서 주요 난제인 공개키 인증 문제를 해결하기 위해 해쉬 함수를 사용하여 계산비용을 줄일 수 있는 트리 기반의 인증기법[1]을 제안하였다. 그러나 이 기법은 공개키 인증을 위해 노드의 수 N에 대해 O(logN)의 수행시간이 필요하고 전송되는 메시지의 양도 O(logN)이 되어 네트워크의 크기에 따라 인증비용이 커지는 문제점이 있다. 이러한 문제를 해결하기 위하여 본 논문에서는 공개키 인증을 위한 안전하고 효율적인 경량의 인증 기법을 제안한다. 제안한 기법은 해쉬 연산과 XOR 연산을 이용하여 네트워크의 크기에 관계없이 상수복잡도의 수행시간과 전송되는 메시지의 양이 상수복잡도인 향상된 공개키 인증을 수행한다.