• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.1
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• pp.86-96
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• 2016

Recently, virtualization is becoming the critical issue in the cloud computing due to its advantages of resource utilization and consolidation. In order to efficiently use virtualization services, several issues should be taken into account, including data reliability, security, and performance. In particular, a high write bandwidth on the virtual machine must be guaranteed to provide fast responsiveness to users. In this study, we implemented a way of visualizing comparison results between the block write pattern of KVM-based virtual machine and that of the real machine. Our final objective is to propose an optimized virtualization environment that enables to accelerate the disk write bandwidth.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.117-123
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• 2013

By exploiting the regular read and write access patterns of embedded SRAM memories inside Viterbi decoder, the memory architecture can be efficiently modified to reduce the power consumption of write operation. According to the experimental results with 65nm CMOS process, the proposed embedded memory used for Viterbi decoder achieves 30.84% of power savings with 8.92% of area overhead compared to the conventional embedded SRAM approaches.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.59-62
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• 2000

As the density of memories increases, unwanted interference between cells and coupling noise between bit-lines are increased and testing high density memories for a high degree of fault coverage can require either a relatively large number of test vectors or a significant amount of additional test circuitry. From now on, conventional test algorithms have focused on faults between neighborhood cells, not neighborhood bit-lines. In this paper, a new algorithm for NPSFs, and neighborhood bit-line sensitive faults (NBLSFs) based on the NPSFs are proposed. Instead of the conventional five-cell and nine-cell physical neighborhood layouts to test memory cells, a three-cell layout which is minimum size for NBLSFs detection is used. To consider faults by maximum coupling noise by neighborhood bit-lines, we added refresh operation after write operation in the test procedure(i.e., write \longrightarrow refresh \longrightarrow read). Also, we present properties of the algorithm, such as its capability to detect stuck-at faults, transition faults, conventional pattern sensitive faults, and neighborhood bit-line sensitive faults.

• Journal of the Semiconductor & Display Technology
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• v.21 no.4
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• pp.86-91
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• 2022

Cache bypassing is a scheme to prevent unnecessary cache blocks from occupying the capacity of the cache for avoiding cache contamination. This method is introduced to alleviate the problems of non-volatile memories (NVMs)-based memory system. However, the prior works have been studied without considering wear-out attack. Malicious writing to a small area in NVMs leads to the failure of the system due to the limited write endurance of NVMs. This paper proposes a novel scheme to prolong the lifetime with higher resistance for the wear-out attack. First, the memory reference pattern is found by modified reuse distance calculation for each cache block. If a cache block is determined as the target of the attack, it is forwarded to higher level cache or main memory without updating the NVM-based cache. The experimental results show that the write endurance is improved by 14% on average and 36% on maximum.

• Proceedings of the Korea Information Processing Society Conference
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• 2009.11a
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• pp.77-78
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• 2009

In this paper, we study a pattern-aware write cache policy using a NAND flash memory in disk-based mobile storage systems. Our work is designed to face a mix of a number of sequential accesses and fewer non-sequential ones in mobile storage systems by redirecting the latter to a NAND flash memory and the former to a disk. Experimental results show that our policy improves the overall I/O performance by reducing the overhead significantly from a non-volatile cache over a traditional one.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.1
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• pp.46-56
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• 1991

In this paper, 16word X 8bit Content Addressable and Reentrant Memory(CARM) is described. This device has 4 operation modes(read, write, match, reentrant). The read and write operation of CARM is like that of static RAM, CARM has the reentrant mode operation where the on chip garbage collection is accomplished conditionally. Thus function can be used for high speed matching unit of dynamic data flow computer. And CARM also can encode matching address sequentially according to therir priority. CARM consists of 8 blocks(CAM cell, Sequential Address Encoder(S.A.E). Reentrant operation. Read/Write control circuit, Data/Mask Register, Sense Amplifier, Encoder. Decoder). Designed DARM can be used in data flow computer, pattern, inspection, table look-up, image processing. The simulation is performed using the QUICKSIM logic simulator and Pspice circuit simulator. Having hierarchical structure, the layout was done using the 3{\;}\mu\textrm{m} n well CMOS technology of the ETRI design rule.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.389-392
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• 2005

In the maskless photolithography based on the Digital Micromirror Device (DMD) by Texas Instruments Inc. (TI), the micromirror array works as a virtual photomask to write patterns directly onto Flat Panel Display (FPD) at high speed with low cost. However, it is neither simple to generate region-based patterns for the micromirror array nor easy to deliver sequences of patterns for the micromirror controller. Moreover, the quality of lithography yields the precise synchronization between generating sequence of patterns and irradiation rate off micromirrors. In this study, the region-based pattern generating system for maskless photolithography is devised. To verify salient features of devised functionalities, the prototype system is implemented and the system is evaluated with actual DMD based photolithography. The results show that proposed pattern generating method is proper and reliable. Moreover, the devised region-based pattern generating system is robust and precise enough to handle any possible user specified mandate and to achieve the quality of photolithography required by FPD manufacturer.

• East Asian mathematical journal
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• v.31 no.4
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• pp.505-525
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• 2015

The purpose of this study is to analyze teaching method of addition and subtraction of whole number in Korea and New Zealand lower grade textbook and to get some suggestive points to develop mathematics curriculum and for a qualitative improvement of textbook. To do this, we will analyze focusing on teaching material, type and method of teaching, cases of real teaching and in the case of New Zealand, we will analyze portfolios together to see what kind of things do they deal with related to addition and subtraction. From these analyzing, the results are as follows: First, the guideline of accomplishment of group of year are stated in 2009 revised curriculum in Korea but it is rough. On the other hand, the level of accomplishment from kindergarten to high school are stated divided by eight kinds of thing in New Zealand curriculum. Second, there were common and different points in the aspect of teaching material. The common points are that both of our Korea and New Zealand are using materials related to real life intimately and the diifferent points are to use technology such as calculator and computer. They are more widely used in New Zealand than our Korea. Third, Korea had used routine method mainly but New Zealand had used method to develop creativity of learner such as to write problem corresponding to expression, posing problem corresponding to information, to complete table and find pattern and to write word problem to explain pattern and so on. Fourth, we could see special calculation strategies in the case of teaching addition and subtraction such as concept of double, compensation, various strategy based on counting of number, addition of the same number, magic square, near-double which are not finding in our mathematics textbook. Fifth, in the New Zealand textbook they had used teaching methods inducing curiosity of learner such as finding message and puzzle problem than solving given problem simply.

• Journal of the Korea Society of Computer and Information
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• v.22 no.4
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• pp.25-32
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• 2017

Recently, the use of NAND flash memory is being increased as a secondary device to displace conventional magnetic disk. NAND flash memory, as one among non-volatile memories, has many advantages such as low power, high reliability, low access latency, and so on. However, NAND flash memory has disadvantages such as erase-before-write, unbalanced operation speed, and limited P/E cycles, unlike conventional magnetic disk. To solve these problems, NAND flash memory mainly adopted FTL (Flash Translation Layer). In particular, garbage collection technique in FTL tried to improve the system lifetime. However, previous garbage collection techniques have a sensitive property of the system lifetime according to write pattern. To solve this problem, we propose BSGC (Balanced Selection-based Garbage Collection) technique. BSGC efficiently selects a victim block using all intervals from the past information to the current information. In this work, SFL (Search First linked List), as the proposed block allocation policy, prolongs the system lifetime additionally. In our experiments, SFL and BSGC prolonged the system lifetime about 12.85% on average and reduced page migrations about 22.12% on average. Moreover, SFL and BSGC reduced the average response time of 16.88% on average.

• 대한상한금궤의학회지
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• v.10 no.1
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• pp.115-124
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• 2018

Objective : The purpose of this paper is to report the improvements of a patient who has suffered from aftereffects following stroke such as dysgraphia and articulation disorder, which is treated by herbal medication based on Shanghanlun disease pattern identification diagnostic system. Methods : According to 'Disease Pattern Identification Diagnostic System based on Shanghanlun Provisions', the patient was diagnosed as Taeyang-byung Gyeolhyung and number 138 provision, and was administered Sohamhyung-tang for 90 days. We recorded the progress of improvements based on the patient's statement and documented the patient's writing Results : The patient can write the letters such as U, 2, ㄹ,ㅇ more clearly and become confident on both writing and speaking. Conclusions : This case shows the effects of Sohamhyung-tang on aftereffects following stroke such as dysgraphia and articulation disorder. It was induced according to the 'Disease Pattern Identification Diagnostic System based on Shanghanlun Provisions' so that it suggest a potential interpretation, which is different with it of the text books Herbal Formula Science and Sanghallonjeonghae, on the provision no. 138. Also the usage of Sohamhyung-tang in this case may support the way far from the diagnosis of oriental neurological medicine, which explain the pathology of stroke as fire-heat(火熱), dampness-phlegm(濕痰), static blood(瘀血) and dual deficiency of qi and blood(氣血兩虛).