• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.101-109
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• 2009

Generally, depth cache and pixel cache of 3D graphics are designed by using write-back scheme for efficient use of memory bandwidth. Also, there are write after read operations of same address or only write operations are occurred frequently in 3D graphics cache. If a cache miss is detected, an access to the external memory for write back operation and another access to the memory for handling the cache miss are operated simultaneously. So on frequent cache miss situations, as the memory access bandwidth limited, the access time of the external memory will be increased due to memory bottleneck problem. As a result, the total performance of the processor or the IP will be decreased, also the problem will increase peak power consumption. So in this paper, we proposed a novel early write back cache architecture so as to solve the problems issued above. The proposed architecture controls the point when to access the external memory as to copy the valid data block. And this architecture can improve the cache performance with same hit ratio and same capacity cache. As a result, the proposed architecture can solve the memory bottleneck problem by preventing intensive memory accesses. We have evaluated the new proposed architecture on 3D graphics z cache and pixel cache on a SoC environment where ARM11, 3D graphic accelerator and various IPs are embedded. The simulation results indicated that there were maximum 75% of performance increase when using various simulation vectors.

• The Transactions of the Korea Information Processing Society
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• v.6 no.11
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• pp.3116-3123
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• 1999

Current disk systems are generally designed to reduce read traffic more effectively. Hence, write traffic of the I/O workload could potentially become a bottleneck of the disk system performance. In order to overcome this problem without much cost, this paper presents using outermost-zone track of multi-zoned recording disk as a secondary disk cache. The proposed disk cache improves the disk system performance by following exploitations: speed difference between block transfer and track transfer, difference in transfer rate between outermost-zone tracks and inner tracks, reduction in the seek time caused by decreasing the number of disk cache tracks, and idle period during burst accesses. In addition, it does not waste the disk space because it allocates the caching space by the cylinder unit. The simulation results show that the proposed system improves 2.54∼3.11 times better in terms of average response time for write operations than existing disk systems..

• Journal of Industrial Technology
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• v.15
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• pp.103-111
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• 1995

In this paper we evaluate the performance of the cached RAID5 which uses the parity cache and the data cache to overcome the small write problem. From the result of the simulation study we show that the cached RAID5 provides performance improvement with reasonable cache size.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.23-30
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• 2016

We report a STT-MRAM write-scheme, in which the length of the write-pulse is determined dynamically by sensing the status of MTJ cells. The proposed scheme can reduce the power consumption by eliminating unnecessary writing current after the switching has occurred. We also propose a reference cell design, which is optimized for the use in write-circuits. The performance of the proposed circuit was verified by SPICE level simulations of the circuit implemented in a $0.13{\mu}m$ CMOS process.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.1
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• pp.136-140
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• 2015

Linux environment that is commonly used at embedded systems supports various file systems as Ext2, FAT, NTFS, etc. The file system that is equiped on the embedded system is mostly implemented on mini hard disk or flash memory. The types of the file system of the system make an effect on the performance of a application programs. The factors of file system performance on a same media are block read, block write and block free time. On these factors, block read and block free time are not so different according to the type of file systems. This paper evaluates the performance benchmark of file systems supported by linux about block allocation and write performance. The results obtained from various experiments shows the characteristics of each file system.

• ETRI Journal
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• v.37 no.1
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• pp.147-156
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• 2015

A typical solid-state drive contains several independent channels that can be operated in parallel. To exploit this channel-level parallelism, a variety of works proposed to split consecutive write sequences into small segments and schedule them to different channels. This scheme exploits the parallelism but breaks the spatial locality of write traffic; thus, it is able to significantly degrade the efficiency of garbage collection. This paper proposes a channel-aware write reordering (CAWR) mechanism to schedule write requests to different channels more intelligently. The novel mechanism encapsulates correlated pages into a cluster beforehand. All pages belonging to a cluster are scheduled to the same channels to exploit spatial locality, while different clusters are scheduled to different channels to exploit the parallelism. As CAWR covers both garbage collection and I/O performance, it outperforms existing schemes significantly. Trace-driven simulation results demonstrate that the CAWR mechanism reduces the average response time by 26% on average and decreases the valid page copies by 10% on average, while achieving a similar hit ratio to that of existing mechanisms.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.4
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• pp.213-225
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• 2007

Flash memory is widely used as a storage device for potable equipments such as digital cameras, MP3 players and cellular phones because of its characteristics such as its large volume and nonvolatile feature, low power consumption, and good performance. However, a block in flash memories should be erased to write because of its hardware characteristic which is called as erase-before-write architecture. The erase operation is much slower than read or write operations. FTL is used to overcome this problem. We compared the performance of the existing FTL algorithms on Windows-based OS. We have developed a tool called FTL APAT in order to gather I/O patterns of the disk and analyze the performance of the FTL algorithms. It is the log buffer scheme with full associative sector translation(FAST) that the performance is best.

• Journal of Internet of Things and Convergence
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• v.8 no.4
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• pp.9-15
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• 2022

NAND flash memory is used as a medium for various storage devices due to its high data processing speed with low power consumption. However, since the read processing speed of data is about 10 times faster than the write processing speed, various studies are being conducted to improve the speed difference. In particular, flash dedicated buffer management policies have been studied to improve write speed. However, SSD(solid state disks), which has recently been used for various purposes, is more vulnerable to read performance than write performance. In this paper, we find out why read performance is slower than write performance in SSD composed of NAND flash memory and study buffer management policies to improve it. The buffer management policy proposed in this paper proposes a method of improving the speed of a flash-based storage device by analyzing the pattern of read data and applying a policy of pre-reading data to be requested in the future from NAND flash memory. It also proves the effectiveness of the read-ahead policy through simulation.

• Proceedings of the IEEK Conference
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• 2000.06c
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• pp.47-50
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• 2000

In this paper, we propose a new destage algorithms, called the Dynamic Adaptive Threshold which determines turn-on and turn-off thresholds dynamically depending on the current write cache occupancy level and the differential rate of the host write requests. For performance evaluation, the proposed algorithm is compared with the wellknown High-Low Water Mark (HLWM) algorithm. Performance tests are fulfilled with our cached RAID 5 simulator. The simulation results show that the proposed algorithm outperforms the HLWM algorithm in terms of response time of host reads and write cache hit ratio under various workloads.

• IEMEK Journal of Embedded Systems and Applications
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• v.14 no.2
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• pp.71-78
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• 2019

As the capacity of SSDs rapidly increases, the amount of DRAM to keep a mapping table size in SSDs becomes very huge. To address a Demand-based FTL (DFTL) scheme that caches part of mapping entries in DRAM is considered to be a feasible alternative. However, owing to its unpredictable behaviors, DFTL fails to provide consistent I/O response times. In this paper, we a) analyze a root cause that results in fluctuation on read latency and b) propose a new demand-based FTL scheme that ensures guaranteed read response time with low write amplification. By preventing mapping evictions while serving reads, the proposed technique guarantees every host read requests to be done in 2 NAND read operations. Moreover, only with 25% of a cache ratio, the proposed scheme improves random write performance and random mixed performance by 1.65x and 1.15x, respectively, over the traditional DFTL.