• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.80-89
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• 2006

The rapid development of process technology and the introduction of new materials not only make it difficult for process control but also as a result increase process variations. These process variations are barriers to successful implementation of design circuits because there are disparities between data on layout and that on wafer. This paper proposes a new design environment to determine the interconnect worstcase with accuracy and speed so that the interconnect effects due to process-induced variations can be applied to designs of $0.13{\mu}m$ and below. Common Geometry and Maximum Probability methods have been developed and integrated into the new worstcase optimization algorithm. The delay time of the 31-stage Ring Oscillator, manufactured in UMC $0.13{\mu}m$ Logic, was measured, and the results proved the accuracy of the algorithm. When the algorithm was used to optimize worstcase determination, the relative error was less than 1.00%, two times more accurate than the conventional methods. Furthermore, the new worstcase design environment improved optimization speed by 32.01% compared to that of conventional worstcase optimizers. Moreover, the new worstcitse design environment accurately predicted the worstcase of non-normal distribution which conventional methods cannot do well.

• Proceedings of the KIPE Conference
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• 2015.07a
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• pp.257-258
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• 2015

본 논문은 최근 태양광 발전 시스템 중 하나로서 주목 받고 있는 차동 전력 조절기의 전력을 최소화 하기위한 LPPT(Least Power Point Tracking)에 관한 논문이다. 기존에 있던 LPPT 방식은 차동 전력 조절기가 부담하는 전력의 총 합을 최소화시키는 방향으로 중앙 부스트 컨버터의 스트링 전류를 제어 하였지만, 본 논문에서는 여러개의 차동 전력 조절기 중 가장 전력을 많이 부담 하게 되는 쪽의 전력을 최소화(worst-case LPPT) 하는 방향으로 스트링 전류를 제어 하는 알고리즘을 제안한다. 이를 PSIM 시뮬레이션과 140W급 하드웨어 프로토 타입으로 Worstcase LPPT 동작을 확인 하였다.