• Steel and Composite Structures
• /
• 제7권3호
• /
• pp.253-262
• /
• 2007

A methodology to design symmetrically laminated fibre-reinforced structures under transverse loads for minimum weight, with manufacturing uncertainty in the ply angle, is described. The ply angle and the ply thickness are the design variables, and the Tsai-Wu failure criteria is the design constraint implemented. It is assumed that the probability of any tolerance value occurring within the tolerance band, compared with any other, is equal, and thus the approach is a worst-case scenario approach. The finite element method, based on Mindlin plate and shell theory, is implemented, and thus effects like bending-twisting coupling are accounted for. The Golden Section method is used as the search algorithm, but the methodology is flexible enough to allow any appropriate finite element formulation, search algorithm and failure criterion to be substituted. In order to demonstrate the procedure, laminated plates with varying aspect ratios and boundary conditions are optimally designed and compared.

• Journal of Computational Design and Engineering
• /
• 제2권4호
• /
• pp.197-205
• /
• 2015

Bladed disk (BLISK) is a vital part in jet engines with a complicated shape which is exclusively machined on a five-axis machine and requires high accuracy of machining. Poor quality of tool orientation (e.g., false tool positioning and unsmooth tool orientation transition) during the five-axis machining may cause collision and machine vibration, which will debase the machining quality and in the worst case sabotage the BLISK. This paper presents a reference plane based algorithm to generate a set of smoothly aligned tool orientations along a tool path. The proposed method guarantees that no collision would occur anywhere along the tool path, and the overall smoothness is globally optimized. A preliminary simulation verification of the proposed algorithm is conducted on a BLISK model and the tool orientation generated is found to be stable, smooth, and well-formed.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제13권6호
• /
• pp.594-607
• /
• 2013

A new efficient analytical eye-diagram determination technique for coupled interconnect lines is presented. Two coupled lines are decoupled into isolated eigen modes; bit blocks for coupled lines, which are defined as a block of consecutive bits, are then represented with decoupled modes. The crosstalk effects within the bit blocks are taken into account. Thereby, the crucial input bit patterns for the worst case eye-diagram determination are modeled mathematically, including inter-symbol interference (ISI). The proposed technique shows excellent agreement with the SPICE-based simulation. Furthermore, it is very computation-time-efficient in the order of magnitude, compared with the SPICE simulation, which requires numerous pseudo-random bit sequence (PRBS) input signals.

• 대한임베디드공학회논문지
• /
• 제3권3호
• /
• pp.136-142
• /
• 2008

Mobile robots can offer services like intelligent monitoring in an indoor environment using network connection with remote users. In this paper, we designed and developed a networked security robot system with various sensors, such as flame detector, gas detector, sound monitoring module, and temperature sensor, etc. The robot can be accessed through a web service and the user can check the status of the environment. Using ADAMS software, we defined the motor specification for a worst-case condition of climbing over a obstacle. We applied the robot system in monitoring office condition.

• 대한임베디드공학회논문지
• /
• 제15권5호
• /
• pp.235-242
• /
• 2020

This paper analyzes the effect of reduced output width of the truncated logarithmic multiplication and application to inferences using convolutional neural networks (CNNs). For small hardware overhead, output width is reduced in the truncated Mitchell multiplier, so that fractional bits in multiplication output are minimized in error-resilient applications. This analysis shows that when reducing output width in the truncated Mitchell multiplier, even though worst-case relative error increases, average relative error can be kept small. When adopting 8 fractional bits in multiplication output in the evaluations, there is no significant performance degradation in target CNNs compared to existing exact and original Mitchell multipliers.

• 제어로봇시스템학회:학술대회논문집
• /
• 제어로봇시스템학회 1995년도 Proceedings of the Korea Automation Control Conference, 10th (KACC); Seoul, Korea; 23-25 Oct. 1995
• /
• pp.424-427
• /
• 1995

In this paper, a control law based on the receding horizon concept which robustly stabilizes time-varying discrete linear systems, is proposed. A dynamic game problem minimizing the worst case performance, is adopted as an optimization problem which should be resolved at every current time. The objective of the proposed control law is to guarantee the closed loop stability and the infinite horizon $H^{\infty}$ norm bound. It is shown that the objective can be achieved by selecting the proper terminal weighting matrices which satisfy the inequality conditions proposed in this paper. An example is included to illustrate the results..

• 제어로봇시스템학회:학술대회논문집
• /
• 제어로봇시스템학회 1999년도 제14차 학술회의논문집
• /
• pp.108-111
• /
• 1999

In this paper, we develope a composite control law for linear systems with norm-bounded time-varying parameter uncertainties, which consists of a basic linear robust control do-signed so as to generate a desired transient time-response for the worst-case parameter variation and a nonlinear modification term designed so as to reduce cautiousness of the linear robust control in an adaptive manner. The proposed controller is established such that the reduction of cautiousness of the linear robust control is well incorporated into the achievement of a good transient behavior.

• 제어로봇시스템학회논문지
• /
• 제13권3호
• /
• pp.263-267
• /
• 2007

This study proposes a new methodology to estimate the traffic capacity of a personal rapid transit(PRT) system. The proposed method comprises three steps. The first step models the guideway network(GN) of PRT as a digraph, where its node and link represent a station and a one-way guideway link between two stations, respectively. Given local vehicle control strategies, the second step formulates the local traffic capacities through the nodes and links of the GN model. The third step estimates the worst-case local traffic demands based on a shortest-path routing algorithm and an empty vehicle allocation algorithm. By comparing the traffic estimates to the local traffic capacities, we can determine the feasibility of the given GN in traffic capacity.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
• /
• pp.137-140
• /
• 2001

This paper shows an asynchronous comparator circuit for 1.2Gbps signal receiver that converts 1.2Gbps data rate input signals with less than 100㎷ swing to on-chip CMOS compatible voltage levels in a 0.35${\mu}{\textrm}{m}$ CMOS process. Folded-cascode nMOS input stage with source-coupled pMOS input stage cover rail-to-rail input common-mode range. Drastic gain-bandwidth increment due to gain-boosting stage with positive-feedback latch as well as wide input common-mode range make designed circuit be suitable for a fully differential signal receiver. HSPICE simulation results show that worst-case sensitivity is less than 20㎷ and maximum propagation delay is 640-psec. And also we verified 3.97㎽ power consumption with 150㎷ differential swing amplitude at 1.2Gbps.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 1999년도 추계종합학술대회 논문집
• /
• pp.340-343
• /
• 1999

In this paper, we propose a wide range PLL(Phase Locked Loop) for 64X CD-ROMs & l0X DVD-ROMs. The frequency locking range of the Proposed PLL is 75MHz~370MHz. To reduce jitters caused by large VCO gain and supply voltage noise, a new V-I converter and a differential delay cell are used in 3-stage ring VCO, respectively. The new V-I converter has a 0.6V ~ 2.5V wide input range. In addition, we propose a new charge pump which has perfect current matching characteristics for the sourcing/sinking current. This new charge pump improves the locking time and the locking range of the PLL. This Chip is implemented in 0.25${\mu}{\textrm}{m}$ CMOS process. It consumes 55㎽ in worst case with a single 2.5V power supply.