• Title/Summary/Keyword: Worst case

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Holistic Scheduling Analysis of a CAN based Body Network System (CAN을 이용한 차체 네트웍 시스템에 대한 Holistic 스케줄링 해석)

  • 신민석;이우택;선우명호
    • Transactions of the Korean Society of Automotive Engineers
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    • v.10 no.5
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    • pp.114-120
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    • 2002
  • In a distributed real-time control system, it is essential to confirm the timing behavior of all tasks because these tasks of each real-time controller have to finish their processes within the specified time intervals called a deadline. In order to satisfy this objective, the timing analysis of a distributed real-time system such as shcedulability test must be performed during the system design phase. In this study, a simple application of CAN fur a vehicle body network system is formulated to apply to a holistic scheduling analysis, and the worst-case execution time (WCET) and the worst-case end-to-end response time (WCRT) are evaluated in the point of holistic system view.

Worst Case Analysis for General Conventional Linear Regulator (일반적인 재래식 선형 전압 조절기의 최악 조건 해석)

  • Lee, Yun-Ki;Kwon, Ki-Ho;Choi, Seung-Woon;Lee, Sang-Kon
    • Aerospace Engineering and Technology
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    • v.8 no.1
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    • pp.162-171
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    • 2009
  • Linear regulator for generating various voltages in satellite electronics is implemented with radiation harden regulator chips or simple linear regulator circuits. For implementing linear regulator circuits, the detail design can be various. But the worst case analysis method and interesting analysis items for the linear regulator circuits can be generalized. So this paper describes and summarizes the general worst case analysis method and interesting analysis items for the conventional linear regulator circuits.

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IC Worst Case Analysis Considered Random Fluctuations on Fabrication Process (제조 공정상 랜덤 특성을 고려한 IC 최악조건 해석)

  • 박상봉;박노경;전흥우;문대철;차균현
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.25 no.6
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    • pp.637-646
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    • 1988
  • The CMOS physical parameters are extracted using by processing models in fabrication steps, processing parameters, fabrication disturbances, control parameters. Statistical CMOS process and device simulator is proposed to evaluate the effect of inherent fluctuations in IC fabrication. Using this simulator, we perform worst case analysis in terms of statistically independent disturbances and compare this proposed method to Monte Carlo method, previous Worst Case method. And simulation results with this proposed method are more accurate than the past worst case analysis. This package is written in C language and runs on a IBM PC AT(OPUS).

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Worst-case optimal feedback control policy for a remote electrical drive system with time-delay

  • Gao, Yu;Zhang, Zheng;Lee, Chang-Goo;Chong, Kil-To
    • Proceedings of the KIEE Conference
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    • 2007.04a
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    • pp.92-94
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    • 2007
  • This paper considers an optimal control problem for a remote control to an electrical drive system with a DC motor. Since it is a linear control system with time-delay subject to unknown but bounded disturbance, we construct a worst-case feedback control policy. This policy can guarantee that, for all admissible uncertain disturbances, the real system state should be in a prescribed neighborhood of a desired value, and the cost functional takes the best guarantee value. The worst-case feedback control policy is allowed to be corrected at one correction point between the initial to the final time, which is equivalent to solving a 1-level min-max problem. Since the min-max problem at the stage does not yield a simple analytical solution, we consider an approximate control policy, which is equivalent and can be solved explicitly m the numerical experiments.

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The Worst-Case Optimal Design of An Interface Circuit for Satellite (Worst Case를 고려한 위성체 접속회로의 최적설계)

  • Lho, Yeung-Hwan;Lee, Sang-Yong
    • Journal of Institute of Control, Robotics and Systems
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    • v.8 no.2
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    • pp.136-141
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    • 2002
  • The electrical characteristics of solid state devices such as BJT(Bipolar Junction Transistor) and MOSFET, etc, are altered by impinging nuclear radiation and temperature in the space environment. This phenomenon is well known and has been studied extensively since the early 1960's when satellites were first being designed and used in the United States. However, the studies and the developments of radiation hardening technologies for the electronic components at the industrial fields in our country has not been popular so far. The worst case design technology in the electrical circuit is required for the appropriate operation of solid state devices in the space environment. In this paper, the interface circuit used in KOMPSAT(Korea Multipurpose Satellite), which is now being operated since the one was launched in 1999, is optimally designed to accomodate the worst case design and radiation effect.

Measuring Method of Worst-case Execution Time by Analyzing Relation between Source Code and Executable Code (소스코드와 실행코드의 상관관계 분석을 통한 최악실행시간 측정 방법)

  • Seo, Yongjin;Kim, Hyeon Soo
    • Journal of Internet Computing and Services
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    • v.17 no.4
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    • pp.51-60
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    • 2016
  • Embedded software has requirements such as real-time and environment independency. The real-time requirement is affected from worst-case execution time of loaded tasks. Therefore, to guarantee real-time requirement, we need to determine a program's worst-case execution time using static analysis approach. However, the existing methods for worst-case execution time analysis do not consider the environment independency. Thus, in this paper, in order to provide environment independency, we propose a method for measuring task's execution time from the source codes. The proposed method measures the execution time through the control flow graph created from the source codes instead of the executable codes. However, the control flow graph created from the source code does not have information about execution time. Therefore, in order to provide this information, the proposed method identifies the relationships between statements in the source code and instructions in the executable code. By parameterizing those parts that are dependent on processors based on the relationships, it is possible to enhance the flexibility of the tool that measures the worst-case execution time.

Worst Case Timing Analysis for DMA I/O Requests in Real-time Systems (실시간 시스템의 DMA I/O 요구를 위한 최악 시간 분석)

  • Hahn Joosun;Ha Rhan;Min Sang Lyul
    • Journal of KIISE:Computer Systems and Theory
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    • v.32 no.4
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    • pp.148-159
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    • 2005
  • We propose a technique for finding the worst case response time (WCRT) of a DMA request that is needed in the schedulability analysis of a whole real-time system. The technique consists of three steps. In the first step, we find the worst case bus usage pattern of each CPU task. Then in the second step, we combine the worst case bus usage pattern of CPU tasks to construct the worst case bus usage pattern of the CPU. This second step considers not only the bus requests made by CPU tasks individually but also those due to preemptions among the CPU tasks. finally, in the third step, we use the worst case bus usage pattern of the CPU to derive the WCRT of DMA requests assuming the fixed-priority bus arbitration protocol. Experimental results show that overestimation of the DMA response time by the proposed technique is within $20\%$ for most DMA request sizes and that the percentage overestimation decreases as the DMA request size increases.

The Worst Performance Analysis of Nnterval Plants : A Conjecture (Interval Plants의 최대평가함수 해석 - 가설)

  • 김영철;허명준
    • 제어로봇시스템학회:학술대회논문집
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    • 1993.10a
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    • pp.168-172
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    • 1993
  • As the worst-case analysis for interval plants, a conjecture whether the supremum of the integral of square error(ISE) is attained at the extreme point such as vertices, Kharitonov vertices, CB segment, and edges is suggested. We present a sufficient condition for which the worst performance index occurs at one ofvertices of uncertain parameter space. Numerical examples are also given.

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Development of Emergency Restoration Scenarios for Railway Accident using Analytic Network Process (네트워크분석적 의사결정기법을 이용한 철도사고 임시복구시나리오 개발)

  • Sung, Deok-Yong;Park, Yong-Gul
    • KSCE Journal of Civil and Environmental Engineering Research
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    • v.31 no.5D
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    • pp.727-737
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    • 2011
  • The emergency restoration scenarios for efficient railway accident management and restoration were developed. The emergency restoration procedures defined by the worst case of emergency restoration and the important events was proposed based on questionnaires from specialists and the result of survey. Via these studies, the railway accident in the tunnel could be the worst case among all railway accident types. Therefore, educations for a restoration team in confined area condition should be planned and performed to recover the worst case accident. In order for the emergency restoration, when a railway accident is occurred, the restoration should be performed in orders of handing collapse of facilities, burying track, and derailment of vehicle in tunnel based on the statistical analysis. The result of priorities were established by the period of restoration. The standard operation system for efficient railway accident management was developed by synthesizing the worst case for rapid emergency restoration, and important events for the standard operation procedures according to each emergency restoration type. Through this study, the restoration operation system of railway accident are recommended. This paper suggests to develop emergency restoration scenarios for the efficient railway accident management and recovery system. The study results will contribute not only for insuring punctuality, but also for minimizing delays from accidents. Therefore, emergency restoration scenarios will play a major role in the SOP for the damage limitation and the prevention of accident spread.

Static Worst-Case Energy and Lifetime Estimation of Wireless Sensor Networks

  • Liu, Yu;Zhang, Wei;Akkaya, Kemal
    • Journal of Computing Science and Engineering
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    • v.4 no.2
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    • pp.128-152
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    • 2010
  • With the advance of computer and communication technologies, wireless sensor networks (WSNs) are increasingly used in many aspects of our daily life. However, since the battery lifetime of WSN nodes is restricted, the WSN lifetime is also limited. Therefore, it is crucial to determine this limited lifetime in advance for preventing service interruptions in critical applications. This paper proposes a feasible static analysis approach to estimating the worstcase lifetime of a WSN. Assuming known routes with a given sensor network topology and SMAC as the underlying MAC protocol, we statically estimate the lifetime of each sensor node with a fixed initial energy budget. These estimations are then compared with the results obtained through simulation which run with the same energy budget on each node. Experimental results of our research on TinyOS applications indicate that our approach can safely and accurately estimate worst-case lifetime of the WSN. To the best of our knowledge, our work is the first one to estimate the worst-case lifetime of WSNs through a static analysis method.