• Transactions of the Korean Society of Automotive Engineers
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• v.19 no.6
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• pp.30-36
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• 2011

The current test methods are insufficient to evaluate and ensure the safety and reliability of vehicle system for all possible dynamic situation including the worst case such as rollover, spin-out and so on. Although the known NHTSA Sine with dwell steering maneuvers are applied for the vehicle performance assessment, they aren't enough to estimate other possible worst case scenarios. Therefore, it is crucial for us to verify the various worst cases including the existing severe steering maneuvers. This paper includes useful worst case based upon the existing worst case scenarios mentioned above and worst case evaluation for vehicle dynamic controller in simulation basis and UCC HILS. The only human steering angle is selected as a design parameter here and optimized to maximize the index function to be expressed in terms of both yaw rate and side slip angle. The obtained scenarios were enough to generate the worst case to meet NHTSA worst case definition. It has been concluded that the new procedure in this paper is adequate to create other feasible worst case scenarios for a vehicle dynamic control system.

• Transactions of the Korean Society of Automotive Engineers
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• v.16 no.6
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• pp.1-9
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• 2008

The current test methods are insufficient to evaluate and ensure the safety and reliability of vehicle system for all possible dynamic situation including the worst case such as rollover, spin-out and so on. Although the known NHTSA J-turn and Fish-hook steering maneuvers are applied for the vehicle performance assessment, they aren't enough to estimate other possible worst case scenarios. Therefore, it is crucial for us to verify the various worst cases including the existing severe steering maneuvers. This paper includes the procedure to search for other useful worst case based upon the existing worst case scenarios mentioned above and its application in simulation basis. The only human steering angle is selected as a design parameter here and optimized to maximize the index function to be expressed in terms of either roll angle or yaw rate. The obtained scenarios were enough to generate the worst case to meet NHTSA worst case definition (ex.2-inch wheel lift). Additionally, as an application, the worst case steering maneuver is acquired for the vehicle to operate with a simple ESP system. It has been concluded that the new procedure in this paper is adequate to create other feasible worst case scenarios for a vehicle system both with an intelligent safety control system and without it.

• Journal of Communications and Networks
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• v.6 no.1
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• pp.78-87
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• 2004

This paper presents deterministic, worst-case analysis of a queueing system whose multiple homogeneous input streams are regulated by the associated leaky buckets and the queueing system that has a single stream regulated by the jumping-window. Queueing delay averaged over all items is used for performance measure, and the worst-case input traffic and the worst-case performance are identified for both queueing systems. For the former queueing system, the analysis explores different phase relations among leaky-bucket token generations. This paper observes how the phase differences among the leaky buckets affect the worst-case queueing performance. Then, this paper relates the worst-case performance of the former queueing system with that of the latter (the single stream case, as in the aggregate streams from many users, whose item arrivals are regulated by one jumping-window). It is shown that the worst-case performance of the latter is identical to that of the former in which all leaky buckets have the same phase and have particular leaky bucket parameters.

• Journal of Computing Science and Engineering
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• v.3 no.1
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• pp.59-71
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• 2009

While the average-case performance is important for general-purpose applications, worst-case performance is crucial for real-time systems to ensure schedulability and reliability. Recent work has shown that simple prefetching techniques such as the Next-N-Line prefetching can benefit both average-case and worst-case performance; however, the improvement on the worstcase execution time (WCET) is rather limited and inefficient. This paper presents two instruction prefetching approaches that are specially designed to enhance the worst-case performance, including the loop-based prefetching and WCET-oriented prefetching. Our experiments indicate that both instruction prefetching techniques can achieve better worst-case execution cycles than the Next-N-Line prefetching while having various impacts on the average-case performance.

• Journal of Computing Science and Engineering
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• v.3 no.4
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• pp.195-215
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• 2009

Worst-case execution time (WCET) analysis is critical for hard real-time systems to ensure that different tasks can meet their respective deadlines. While significant progress has been made for WCET analysis of instruction caches, the data cache timing analysis, especially for set-associative data caches, is rather limited. This paper proposes an approach to safely and tightly bounding data cache performance by computing the worst-case stack distance of data cache accesses. Our approach can not only be applied to direct-mapped caches, but also be used for set-associative or even fully-associative caches without increasing the complexity of analysis. Moreover, the proposed approach can statically categorize worst-case data cache misses into cold, conflict, and capacity misses, which can provide useful insights for designers to enhance the worst-case data cache performance. Our evaluation shows that the proposed data cache timing analysis technique can safely and accurately estimate the worst-case data cache performance, and the overestimation as compared to the observed worst-case data cache misses is within 1% on average.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.5B
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• pp.270-276
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• 2007

The proposed LDS(Link-status Dependent Scheduling) algorithm in HR-WPAN(High Rate-Wireless Personal Area Network) up to now aims at doing only throughput elevation of the whole network, when the crucial device is connected with worst-link relatively, throughput of this device becomes aggravation. The proposed the WGS(Worst-case Guaranteed Scheduling) algorithm in this paper guarantees throughput of the device which is connected with worst-link in a certain degree as maintaining throughput of all devices identically even if a link-status changes, decreases delay of the whole network more than current LDS algorithm. Therefore proposed WGS algorithm in this paper will be useful in case of guaranteeing throughput of a device which is connected worst-link in a certain degree in a design of HR-WPAN hereafter.

• Journal of Computing Science and Engineering
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• v.5 no.1
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• pp.1-18
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• 2011

As the first step toward real-time multi-core computing, this paper presents a novel approach to bounding the worst-case performance for threads running on multi-core processors with shared L2 instruction caches. The idea of our approach is to compute the worst-case instruction access interferences between different threads based on the program control flow information of each thread, which can be statically analyzed. Our experiments indicate that the proposed approach can reasonably estimate the worst-case shared L2 instruction cache misses by considering the inter-thread instruction conflicts. Also, the worst-case execution time (WCET) of applications running on multi-core processors estimated by our approach is much better than the estimation by simply assuming all L2 instruction accesses are misses.

• Journal of Computing Science and Engineering
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• v.5 no.2
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• pp.131-140
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• 2011

Different cores typically share the last-level cache in a multi-core processor. Threads running on different cores may interfere with each other. Therefore, the multi-core worst-case execution time (WCET) analyzer must be able to safely and accurately estimate the worst-case inter-thread cache interference. This is not supported by current WCET analysis techniques that manly focus on single thread analysis. This paper presents a novel approach to analyze the worst-case cache interference and bounding the WCET for threads running on multi-core processors with shared L2 instruction caches. We propose to use an interference matrix to model inter-thread interference, on which basis we can calculate the worst-case inter-thread cache interference. Our experiments indicate that the proposed approach can give a worst-case bound less than 1%, as in benchmark fib-call, and an average 16.4% overestimate for threads running on a dual-core processor with shared-L2 cache. Our approach dramatically improves the accuracy of WCET overestimatation by on average 20.0% compared to work.

• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.249-251
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• 2007

The proposed LDS(Link-status Dependent Scheduling) algorithm in HR-WPAN up to now aims at doing only throughput elevation of the whole network, when the crucial DEV(Device) is connected with worst-link relatively, throughput of this DEV becomes aggravation, The proposed the WGS(Worst-case Guaranteed Scheduling) _algorithm in this paper guarantees throughput of the DEV which is connected with worst-link in a certain degree as maintaining throughput of all DEVs identically even if a link-status changes, decreases delay of the whole network more than current LDS algorithm Therefore proposed WGS algorithm in this paper will be useful in case of guaranteeing throughput of a DEV which is connected worst-link in a certain degree in a design of HR-WPAN hereafter.

• Aerospace Engineering and Technology
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• v.7 no.2
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• pp.58-66
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• 2008

In the space environment, many other things to design electronic circuits should be considered with respect to commercial circuit design. The first thing is that electronics in space are likely to be exposed to radiation effects and the second thing is that it is impossible to repair or replace electronic parts after once spacecraft was launched. In this severe situation, very strict and tight worst case analysis conditions should be applied to the electronics in space environment to do its own function well without any problems during the overall mission period. So this paper summarizes worst case input conditions and methods which are specified in the ESA Worst Case Analysis Specification (ECSS-Q-30-01A) and proposes the results of Worst Case Analysis for one simple electronic circuit which is implemented at a real On-Board Computer in the Low Earth Orbit Satellite.