• Management Science and Financial Engineering
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• v.17 no.1
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• pp.95-116
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• 2011

This paper considers a flowshop scheduling problem where a customer orders multiple products (jobs) from a production facility. The objectives are to minimize makespan and to minimize the sum of order (batch) completion times. The order cannot be shipped unless all the products in the order are manufactured. This problem was motivated by numerous real world problems encountered by a variety of manufacturers. For the makespan objective, we develop an optimal solution procedure which runs in polynomial time. For the sum of order completion time objective, we establish the complexity of the problem including several special cases. Then, we introduce a simple heuristic and find an asymptotically tight worst case bound on relative error. Finally, we conclude the paper with some implications.

• Journal of the Korean Operations Research and Management Science Society
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• v.25 no.1
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• pp.27-36
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• 2000

We perform a computational complexity analysis of a heuristic algotithm proposed in the literature for the combinatorial optimization problems extended with a single side-constraint. This algorithm, although such a view was not given in the original work, is a disguised version of an optimal Lagrangian dual solution technique. It also has been observed to be a very efficient heuristic producing near-optimal solutions for the primal problems in some experiments. Especially, the number of iterations grows sublinearly in terms of the network node size so that the heuristic seems to be particularly suitable for the applicatons such as routing with semi-real time requirements. The goal of this paper is to establish a polynomal worst-case complexity of the algorithm. In particular, the obtained complexity bound suports the sublinear growth of the required iterations.

• Journal of the Semiconductor & Display Technology
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• v.9 no.2
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• pp.15-20
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• 2010

This paper deals with minimizing layout area of FPGA design. FPGAs are becoming increasingly important in the design of ASICs since they provide both large scale integration and user-programmability. This paper describes a method to obtain tight bound on the worst-case increase in area when drivers are introduced along many long wires in a layout. The area occupied by minimum-area embedding for a circuit can depend on the aspect ratio of the bounding rectangle of the layout. This paper presents a separator-based area-optimal embeddings for FPGA graphs in rectangles of several aspect ratios which solves the longest path problem in the constraint graph.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.11
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• pp.573-580
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• 2001

When tasks access shared resources in real-time systems, the unbounded priority inversion may occur. In such cases it is impossible to guarantee the schedulability of real-time tasks. Several resource access protocols have been proposed to bound the duration of priority inversion and sufficient conditions are given to guarantee the schedulability of periodic task set. In this paper, we show an improved sufficient condition for schedulability when the dynamic priority ceiling protocol is used. Our approach exploits the fact that a lower priority task can continue to execute as far as the higher priority tasks do not miss their deadlines. This permitting execution time of the higher priority tasks for a lower priority task can be excluded from the worst-case blocking time of the higher priority tasks. Since the worst-case blocking time of tasks can be reduced, the sufficient condition for schedulability of dynamic priority ceiling protocol becomes further tight.

• Journal of KIISE:Computing Practices and Letters
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• v.11 no.1
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• pp.15-25
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• 2005

Embedded systems have a set of tasks to execute. These tasks can be implemented either on application specific hardware or as software running on a specific processor. The design of an embedded system involves the selection of hardware software resources, Partition of tasks into hardware and software, and performance evaluation. An accurate estimation of execution time for extreme cases (best and worst case) is important for hardware/software codesign. A tighter estimation of the execution time bound nay allow the use of a slower processor to execute the code and may help lower the system cost. In this paper, we consider an ARM-based embedded system and developed a tool to estimate the tight boundary of execution time of a task with loop bounds and any additional program path information. The tool we developed is based on an exiting timing analysis tool named 'Cinderella' which currently supports i960 and m68k architectures. We add a module to handle ARM ELF object file, which extracts control flow and debugging information, and a module to handle ARM instruction set so that the new tool can support ARM processor. We validate the tool by comparing the estimated bound of execution time with the run-time execution time measured by ARMulator for a selected bechmark programs.

• Journal of KIISE:Information Networking
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• v.28 no.3
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• pp.447-453
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• 2001

In this paper, we consider the scheduling of SE(switching element)-disjoint multicasting in photonic Banyan-type switching networks constructed with directional couplers. This ensures that at most, one connection holds each SE in a given time thus, neither crosstalk nor blocking will arise in the network. Such multicasting usually takes several routing rounds hence, it is desirable to keep the number of rounds(i.e., scheduling length) to a minimum. We first present the necessary and sufficient condition for connections to pass through a common SE(i.e., make crosstalk) in the photonic Banyan-type networks capable of supporting one-to-many connections. With definition of uniquely splitting a multicast connection into distinct subconnections, the crosstalk relationship of a set of connections is represented by a graph model. In order to analyze the worst case crosstalk we characterize the upper bound on the degree of the graph. The successor paper(Part II)[14] is devoted to the scheduling algorithm and the upper bound on the scheduling length. Comparison with related results is made in detail.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.691-694
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• 2003

This paper describes how to use Profibus networks to support real-time industrial communications, that is, how to ensure the transmission of real-time messages within a maximum bound time. Profibus is based on a simplified timed token protocol, which is a well-proved solution for the real-time communication systems. However, Profibus differs from the timed token protocol, thus the usual timed token protocol has to be modified in order to be applied in Profibus. In fact, the real-time solutions for networks based on the timed token protocol rely on the possibility of allocating specific bandwidth for the real-time traffic. This means that a minimum amount of time to transmit the real-time messages is always guaranteed whenever each token is arrived. In other words, with the Profibus protocol, at least, one real-time message should be transmitted per every token visit in the worst case. It is required to control medium access properly to satisfy the message deadlines. In this paper, we have presented how to obtain the optimal network parameter for the Profibus protocol. The selected network parameter is valid regardless of the behavior of asynchronous messages.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.29 no.5 s.236
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• pp.689-697
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• 2005

This paper presents the reliability estimation of door hinge for home appliances, which consists of bushing and shaft. The predominant failure mechanism of bushing made of polyoxymethylene(POM) is brittle fracture due to decrease of strength caused by voids existing, and that of shaft made of acrylonitrile-butadiene-styrene(ABS) is creep due to plastic deformation caused by excessive temperature and lowering of glass transition temperature by absorbed moisture. Since the brittle fracture of bushing is overstress failure mechanism, the load-strength interference model is used to estimate the failure rate of it along with failure analysis. By the way, the creep of shaft is wearout failure mechanism, and an accelerated life test is then planned and implemented to estimate its lifetime. Through the technical review about failure mechanism, temperature and humidity are selected as accelerating variables. Assuming Weibull lifetime distribution and Eyring model, the life-stress relationship and acceleration factor, $B_{10}$ life and its lower bound with $90\%$ confidence at worst case use condition are estimated by analyzing the accelerated life test data.

• Proceedings of the Korean Reliability Society Conference
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• 2004.07a
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• pp.303-311
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• 2004

This paper presents the reliability estimation of door hinge for home appliances, which consists of bushing and shaft. The predominant failure mechanism of bushing made of polyoxymethylene(POM) is brittle fracture due to decrease of strength caused by voids existing, and that of shaft made of acrylonitrile-butadiene-styrene(ABS) is creep due to plastic deformation caused by excessive temperature and lowering of glass transition temperature by absorbed moisture. Since the brittle fracture of bushing is overstress failure mechanism, the load-strength interference model is used to estimate the failure rate of it along with failure analysis. By the way, the creep of shaft is wearout failure mechanism, and an accelerated life test is then planned and implemented to estimate its lifetime. Through the technical review about failure mechanism, temperature and humidity are selected as accelerating variables. Assuming Weibull lifetime distribution and Eyring model, the life-stress relationship and acceleration factor, B$_{10}$ life and its lower bound with 90% confidence at worst case use condition are estimated by analyzing the accelerated life test data.a.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.5C
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• pp.486-495
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• 2002

In this paper, we propose a delay reduction method for frame-based packet transmit scheduling algorithm. A high-speed network such as ATM network has to provide some performance guarantees such as bandwidth and delay bound. Framing strategy naturally guarantees bandwidth and enables simple rate-control while having the inherently bad delay characteristics. The proposed delay reduction method uses the same hierarchical frame structure as HRR (Hierarchical Round-Robin) but does not use the static priority scheme such as round-robin. Instead, we use a dynamic priority change scheme so that the delay unfairness between wide bandwidth connection and narrow bandwidth connection can be eliminated. That is, we use FIFO (First-In First-Out) concept to effectively reduce the occurrence of worst-case delay and to enhance delay distribution. We compare the performance for the proposed algorithm with that of HRR. The analytic and simulation results show that HFIFO inherits almost all merits of HRR with fairly better delay characteristics.