• 한국통신학회논문지
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• 제38A권8호
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• pp.644-649
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• 2013

광기록 정보저장장치에서 인코딩된 시퀀스의 DC-억압을 위해 Guided Scrambling 기법이 널리 사용된다. 후보 코드시퀀스 중 최적의 DC-억압 코드를 선택하기 위해 digital sum value (DSV)의 함수로 정의된 기준을 사용한다. 이 중 minimum DSV (MDSV), minimum squared weight (MSW), minimum threshold overrun (MTO) 등이 널리 사용된다. 본 연구에서는 MDSV, MSW, MTO 기준을 채택하는 GS 코딩 알고리즘과 동등한 정수계획법 모형을 제안한다. 개발된 MDSV 정수계획법 모형을 MaxMin 형태의 모형으로 확장하여 스크램블링 다항식과 제어 비트에 따른 MDSV GS 코딩의 최악 성능을 평가할 수 있는 모형을 개발하였다. 모의실험에서는 다수의 스크램블링 다항식 및 제어비트 조합에 대하여 MDSV 최악 성능을 계산하였다.

• 한국경영과학회지
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• 제15권2호
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• pp.97-104
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• 1990

The problem is a variation of the weighted set-covering problem (SCP) which requires the minimum-cost cover to be self-covering. It is shown that direct extension of the well-known greedy heuristic for SCP can have an arbitrarily large error in the worst case. It remains an open question whther these exists a greedy heuristic with a finite error bound.

• Management Science and Financial Engineering
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• 제13권2호
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• pp.47-77
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• 2007

This paper considers a scheduling problem where a customer orders multiple products(jobs) from a production facility. The objective is to minimize the sum of the order(batch) completion times. While a machine can process only one job at a time, multiple machines can simultaneously process jobs in a batch. Although each job has a unique processing time, we consider the case where batch processing times are identical. This simplification allows us to develop heuristics with improved performance bounds. This problem was motivated by a real world problem encountered by foreign electronics manufacturers. We first establish the complexity of the problem. For the two parallel machine case, we introduce two simple but intuitive heuristics, and find their worst case relative error bounds. One bound is tight and the other bound goes to 1 as the number of orders goes to infinity. However, neither heuristic is superior for all instances. We extend one of the heuristics to an arbitrary number of parallel machines. For a fixed number of parallel machines, we find a worst case bound which goes to 1 as the number of orders goes to infinity. Then, a tighter bound is found for the three parallel machine case. Finally, the heuristics are empirically evaluated.

• Journal of Computing Science and Engineering
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• 제5권2호
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• pp.131-140
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• 2011

Different cores typically share the last-level cache in a multi-core processor. Threads running on different cores may interfere with each other. Therefore, the multi-core worst-case execution time (WCET) analyzer must be able to safely and accurately estimate the worst-case inter-thread cache interference. This is not supported by current WCET analysis techniques that manly focus on single thread analysis. This paper presents a novel approach to analyze the worst-case cache interference and bounding the WCET for threads running on multi-core processors with shared L2 instruction caches. We propose to use an interference matrix to model inter-thread interference, on which basis we can calculate the worst-case inter-thread cache interference. Our experiments indicate that the proposed approach can give a worst-case bound less than 1%, as in benchmark fib-call, and an average 16.4% overestimate for threads running on a dual-core processor with shared-L2 cache. Our approach dramatically improves the accuracy of WCET overestimatation by on average 20.0% compared to work.

• 산업경영시스템학회지
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• 제32권3호
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• pp.188-193
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• 2009

본 논문은 조립과 분리시스템이 혼합된 Fork-and-Join 시스템에서의 일정계획문제를 고려하고 있다. 최초 단계에서는 구성품단위로 분리가 발생하고 두 번째 단계에서는 부품생산단계에서 각 부품 또는 구성품이 서로 다른 설비와 경로를 통해 독립적으로 생산된 후 최종 조립단계로 이동하게 되고, 그곳에서 조립공정을 통해 제품으로 완성된다. 본 논문에서는 이러한 Fork-and-Join 시스템에서 최종완료시간(makespan)을 최소화 할 수 있는 발견적 해법을 제안하고 이 해법의 최악오차한계(worst-case error bound)가 2라는 것을 증명한다. 또한, 제안된 문제의 효과적인 3가지 하한값(lower bound)을 제시하고 다양한 수치실험을 통해 제안된 발견적 해법의 결과와 하한값과의 비교를 통해 제안된 해법이 성능이 우수함을 증명한다.

• Journal of Communications and Networks
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• 제16권1호
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• pp.45-55
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• 2014

The paper investigates the problem of designing the multiple-antenna relay in a two-way relay network by taking into account the imperfect channel state information (CSI). The objective is to design the multiple-antenna relay based upon the CSI estimates, where the estimation errors are included to attain the robust design under the worst-case philosophy. In particular, the worst-case transmit power at the multiple-antenna relay is minimized while guaranteeing the worst-case quality of service requirements that the received signal-to-noise ratio (SNR) at both sources are above a prescribed threshold value. Since the worst-case received SNR expression is too complex for subsequent derivation and processing, its lower bound is explored instead by minimizing the numerator and maximizing the denominator of the worst-case SNR. The aforementioned problem is mathematically formulated and shown to be nonconvex. This motivates the pursuit of semidefinite relaxation coupled with a randomization technique to obtain computationally efficient high-quality approximate solutions. This paper has shown that the original optimization problem can be reformulated and then relaxed to a convex problem that can be solved by utilizing suitable randomization loop. Numerical results compare the proposed multiple-antenna relay with the existing nonrobust method, and therefore validate its robustness against the channel uncertainty. Finally, the feasibility of the proposed design and the associated influencing factors are discussed by means of extensive Monte Carlo simulations.

• Journal of the Korean Society for Industrial and Applied Mathematics
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• 제14권2호
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• pp.93-111
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• 2010

The purpose of this paper is to obtain new complexity results for a second-order cone optimization (SOCO) problem. We define a proximity function for the SOCO by a kernel function. Furthermore we formulate an algorithm for a large-update primal-dual interior-point method (IPM) for the SOCO by using the proximity function and give its complexity analysis, and then we show that the new worst-case iteration bound for the IPM is $O(q\sqrt{N}(logN)^{\frac{q+1}{q}}log{\frac{N}{\epsilon})$, where $q{\geqq}1$.

• Industrial Engineering and Management Systems
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• 제14권1호
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• pp.22-31
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• 2015

In this paper, a two-stage hybrid flow shop problem is considered. Specifically, there exist identical parallel machines at stage 1 and two dedicated machines at stage 2, and the objective of the problem is to minimize makespan. After being processed by any machine at stage 1, a job must be processed by a specific machine at stage 2 depending on the job type, and one type of jobs can have different processing times on each machine. First, we introduce the problem and establish complexity of several variations of the problem. For some special cases, we develop optimal polynomial time solution procedures. Then, we establish some simple lower bounds for the problem. In order to solve this NP-hard problem, three heuristics based on simple rules such as the Johnson's rule and the LPT (Longest Processing Time first) rule are developed. For each of the heuristics, we provide some theoretical analysis and find some worst case bound on relative error. Finally, we empirically evaluate the heuristics.

• Journal of applied mathematics & informatics
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• 제18권1_2호
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• pp.383-391
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• 2005

The paper is devoted to some flow shop scheduling problems, where job processing times are defined by functions dependent on their positions in the schedule. An example is constructed to show that the classical Johnson's rule is not the optimal solution for two different models of the two-machine flow shop scheduling to minimize makespan. In order to solve the makespan minimization problem in the two-machine flow shop scheduling, we suggest Johnson's rule as a heuristic algorithm, for which the worst-case bound is calculated. We find polynomial time solutions to some special cases of the considered problems for the following optimization criteria: the weighted sum of completion times and maximum lateness. Some furthermore extensions of the problems are also shown.

• Journal of Computing Science and Engineering
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• 제9권4호
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• pp.177-189
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• 2015

High-performance processors using Non-Uniform Cache Architecture (NUCA) are increasingly used to deal with the growing wire delays in multicore/manycore processors. Due to the convergence of high-performance computing with embedded computing, NUCA caches are expected to benefit high-end embedded systems as well. However, for real-time systems that use multicore processors with NUCA caches, it is crucial to bound worst-case execution time (WCET) accurately and safely. In this paper, we developed a WCET analysis approach by considering the effect of static NUCA caches on WCET. We compared the WCET in real-time applications with different topologies of static NUCA caches. Our experimental results demonstrated that the static NUCA cache could improve the worst-case performance of realtime applications using multicore processor compared to the cache with uniform access time.