• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.1
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• pp.53-60
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• 2004

This work describes a l0b 150 MSample/s CMOS pipelined A/D converter (ADC) based on advanced bootsuapping techniques for higher input bandwidth than a sampling rate. The proposed ADC adopts a typical multi-step pipelined architecture, employs the merged-capacitor switching technique which improves sampling rate and resolution reducing by $50\%$ the number of unit capacitors used in the multiplying digital-to-analog converter. On-chip current and voltage references for high-speed driving capability of R & C loads and on-chip decimator circuits for high-speed testability are implemented with on-chip decoupling capacitors. The proposed AU is fabricated in a 0.18 um 1P6M CMOS technology. The measured differential and integral nonlinearities are within $-0.56{\~}+0.69$ LSB and $-1.50{\~}+0.68$ LSB, respectively. The prototype ADC shows the signal-to-noise-and-distortion ratio (SNDR) of 52 dB at 150 MSample/s. The active chip area is 2.2 mm2 (= 1.4 mm ${\times}$ 1.6 mm) and the chip consumes 123 mW at 150 MSample/s.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.55-64
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• 2006

This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is $3.3mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.65-73
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• 2006

This work presents a 14b 200KS/s $0.87mm^2$ 1.2mW 0.18um CMOS algorithmic A/D converter (ADC) for intelligent sensors control systems, battery-powered system applications simultaneously requiring high resolution, low power, and small area. The proposed algorithmic ADC not using a conventional sample-and-hold amplifier employs efficient switched-bias power-reduction techniques in analog circuits, a clock selective sampling-capacitor switching in the multiplying D/A converter, and ultra low-power on-chip current and voltage references to optimize sampling rate, resolution, power consumption, and chip area. The prototype ADC implemented in a 0.18um 1P6M CMOS process shows a measured DNL and INL of maximum 0.98LSB and 15.72LSB, respectively. The ADC demonstrates a maximum SNDR and SFDR of 54dB and 69dB, respectively, and a power consumption of 1.2mW at 200KS/s and 1.8V. The occupied active die area is $0.87mm^2$.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.17-26
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• 2016

This work proposes a 12b 60MS/s 0.18um CMOS Flash-SAR ADC for various systems such as wireless communications and portable video processing systems. The proposed Flash-SAR ADC alleviates the weakness of a conventional SAR ADC that the operation speed proportionally increases with a resolution by deciding upper 4bits first with a high-speed flash ADC before deciding lower 9bits with a low-power SAR ADC. The proposed ADC removes a sampling-time mismatch by using the C-R DAC in the SAR ADC as the combined sampling network instead of a T/H circuit which restricts a high speed operation. An interpolation technique implemented in the flash ADC halves the required number of pre-amplifiers, while a switched-bias power reduction scheme minimizes the power consumption of the flash ADC during the SAR operation. The TSPC based D-flip flop in the SAR logic for high-speed operation reduces the propagation delay by 55% and the required number of transistors by half compared to the conventional static D-flip flop. The prototype ADC in a 0.18um CMOS demonstrates a measured DNL and INL within 1.33LSB and 1.90LSB, with a maximum SNDR and SFDR of 58.27dB and 69.29dB at 60MS/s, respectively. The ADC occupies an active die area of $0.54mm^2$ and consumes 5.4mW at a 1.8V supply.

• Journal of the Korean GEO-environmental Society
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• v.1 no.1
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• pp.5-12
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• 2000

Mudstone, found Du-Ho Dong and around there in Po-Hang, is used as construction material. When it is exposed to the air and contacts with water, the strength is decreased rapidly and then it causes a lot of problems. In the field, clay soils with $K_o$ condition have anisotropic characteristics which behave differently according to the change of principal stress direction. In this study, $K_o$ consolidation is performed to make the completely weathered mudstone under the same conditions of construction place. Then, the triaxial compression test is performed at different shear velocity and anisotropy by sampling degree and the stress - strain behavior is shown the strain softening behavior. The stress - strain relationship from triaxial compression test is compared with the prediction value of Cam-clay model. From the results of tests, $K_o$ value decreases with the increase of sampling degree. Generally the behavior of $K_o$ consolidated specimen shows work-softening characteristic. The trend of behaviour of the measured is nearly to same to the predicted by Cam-clay model. But the measured value of deviator stress is very higher than the predicted. Therefore, Cam-clay model was not appropriate to the completely weathered mudstone consolidated with $K_o$ condition in Pohang region.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.27-35
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• 2008

This work proposes a 14b 150MS/s 0.13um CMOS ADC for SDR systems requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC employs a calibration-free four-step pipeline architecture optimizing the scaling factor for the input trans-conductance of amplifiers and the sampling capacitance in each stage to minimize thermal noise effects and power consumption at the target resolution and sampling rate. A signal- insensitive 3-D fully symmetric layout achieves a 14b level resolution by reducing a capacitor mismatch of three MDACs. The proposed supply- and temperature- insensitive current and voltage references with on-chip RC filters minimizing the effect of switching noise are implemented with off-chip C filters. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates a measured DNL and INL within 0.81LSB and 2.83LSB, at 14b, respectively. The ADC shows a maximum SNDR of 64dB and 61dB and a maximum SFDR of 71dB and 70dB at 120MS/s and 150MS/s, respectively. The ADC with an active die area of $2.0mm^2$ consumes 140mW at 150MS/s and 1.2V.

• Journal of Animal Science and Technology
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• v.59 no.5
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• pp.10.1-10.11
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• 2017

Background: Transfer of pesticides from environment to animal products is inevitable, so the purpose of the present work was to evaluate phosalone consumption via feeding with or without sodium bentonite (SB) on performance, blood metabolites and its transition to milk of Iranian Baluchi sheep. Methods: Twenty Baluchi ewes were divided into four treatments (P1 as control, P2, P3, and P4) of five animals in which phosalone, an organophosphate pesticide, was given via diet (only for P2 and P3) at a dose of 280 mg/sheep/day for 63 consecutive days. The SB (32 g/sheep/day; for P3 and P4) was also evaluated for its ability to reduce deleterious effects of phosalone in the sheep diets. The control group (P1) did not receive any phosalone and SB during the experiment. Sampling was conducted in two periods of time including weeks 5 and 9. Results: Phosalone residues were observed in the milk samples of P2 and P3 groups during two sampling periods. During period 1, the transfer rate of phosalone from feed to milk was 0.23 and 0.02%, respectively for the contaminated diets (P2 and P3), which is relatively similar to period 2 (0.22 and 0.02%). Only 0.34 (period 1) and 0. 36% (period 2) of phosalone residue are excreted in the feces of P2 group following its daily consumption. Transfer of phosalone from feed to milk was affected (P < 0.05) by the dietary inclusion of a commercial SB, as it (SB) decreased excretion of phosalone via milk (P3). The phosalone and SB alone or together had no significant effect (P > 0.05) on the dry matter intake (DMI) and body weight (BW) gain, but feed efficiency, milk production, milk fat, dry matter (DM) and organic matter (OM) digestibility, acetylcholinesterase (AChE) inhibitory activity, hemoglobin (Hb), red blood cell (RBC), serum glutamic pyruvic transaminase (SGPT), serum glutamic oxaloacetic transaminase (SGOT), albumin and mean corpuscular hemoglobin concentration (MCHC) affected by the treatments in period 1 or 2 (P < 0.05). The Hb, RBC, and MCHC were significantly decreased (P < 0.05) by about 9.72, 20.77, and 9.71%, respectively in the group P2 as compared to those of the control group during period 1. The AChE inhibitory activity (period 1 and 2) significantly increased when phosalone administered via the diet (P < 0.05). Conclusions: Although there were no adverse effects on the performance of sheep following the intake of phosalone alone (P2 vs. P1), but other research on the long and short times to the phosalone in high and low doses with more animals is suggested. Overall, compared to the control group, addition of SB in the diet of sheep improved nutrient digestibility, animal performance, and milk health.

• Journal of Korean Society of Occupational and Environmental Hygiene
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• v.17 no.1
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• pp.43-52
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• 2007

This study was designed to investigate the difference of airborne lead concentration by type of lead industries and type of lead exposure and to evaluate their association with lead biomarkers of lead workers in 11 lead using industries. Total of 182 lead workers (male: 167, female: 15) from 11 lead industries were participated for this study from March, 2004 to August, 2005. Airborne lead concentration were measured by representative personal sampling of workers in each unit workplace and applied same concentration value to the workers in the same unit workplace who did not measure their airborne lead with personal air sampling. Tibia lead, blood lead, zinc protoporphyrin in whole blood, ${\delta}$-aminolevulinic acid in urine, hemoglobin and hematocrit were selected as study variables of indices of lead exposure. Information about type of lead exposure (fume or non-fume other), age, work duration, smoking & drinking habit were also collected. Significant differences were seen in the means of zinc protoporphyrin, blood lead and tibia lead in lead workers by different airborne lead concentration in workplace. While blood lead and tibia lead in lead workers were significantly higher in secondary smelting than other types of lead industries, zinc protoporphyrin, ${\delta}$-aminolevulinic acid in urine and airborne lead concentration were significantly higher in litharge manufacturing. While the mean blood lead was significantly higher in the lead workers working in fume type unit workplace than those of non-fume lead workers, the mean airborne lead concentration of fume workers was significantly lower than non-fume lead workers. In the multiple regression analysis of airborne lead concentration and the type of lead exposure on tibia lead and lead exposure indices after adjustment of related covariates, airborne lead concentration was statistically significantly associated with blood lead and tibia lead, but the type of lead exposure was only associated with blood lead. To verify the causal association of airborne lead concentration on blood lead and tibia lead, further studies are needed.

• Journal of the Korea Computer Graphics Society
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• v.23 no.1
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• pp.25-32
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• 2017

This paper proposes a novel acceleration method for particle based large scale fluid simulation. Traditional particle-based fluid simulation has been implemented by interacting with physical quantities of neighbor particles through the Smoothed Particle Hydrodynamics(SPH) technique[1]. SPH method has the characteristic that there is no visible change compared to the computation amount in a part where the particle movement is small, such as a calm surface or inter-fluid. This becomes more prominent as the number of particles increases. Previous work has attempted to reduce the amount of spare computation by adaptively dividing each part of the fluid. In this paper, we propose a technique to calculate the motion of the entire particles by using the physical quantities of the near sampled particles by sampling the particles inside the fluid at regular intervals and using them as reference points of the fluid motion. We propose a technique to adaptively generate a triangle map based on the position of the sampled particles in order to efficiently search for nearby particles, and we have been able to interpolate the physical quantities of particles using the barycentric coordinate system. The proposed acceleration technique does not perform any additional correction for two classes of fluid particles. Our technique shows a large improvement in speed as the number of particles increases. The proposed technique also does not interfere with the fine movement of the fluid surface particles.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.4
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• pp.16-24
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• 2002

This work describes a 10b 120 MSample/s CMOS pipelined A/D converter(ADC) based on a merged-capacitor switching(MCS) technique for high signal processing speed and high resolution. The proposed ADC adopts a typical multi-step pipelined architecture to optimize sampling rate, resolution, and chip area, and employs a MCS technique which improves sampling rate and resolution reducing the number of unit capacitor used in the multiplying digital-to-analog converter (MDAC). The proposed ADC is designed and implemented in a 0.25 um double-poly five-metal n-well CMOS technology. The measured differential and integral nonlinearities are within ${\pm}$0.40 LSB and ${\pm}$0.48 LSB, respectively. The prototype silicon exhibits the signal-to-noise-and-distortion ratio(SNDR) of 58 dB and 53 dB at 100 MSample/s and 120 MSample/s, respectively. The ADC maintains SNDR over 54 dB and the spurious-free dynamic range(SFDR) over 68 dB for input frequencies up to the Nyquist frequency at 100 MSample/s. The active chip area is 3.6 $mm^2$(＝ 1.8 mm ${\times}$ 2.0 mm) and the chip consumes 208 mW at 120 MSample/s.