• 한국방사선학회논문지
• /
• 제17권5호
• /
• pp.725-733
• /
• 2023

본 연구의 목적은 가상 그리드 소프트웨어(VGS)의 유효성을 평가하기 방법으로 이동형 그리드를 사용하지 않은 상태에서 VGS를 사용할 때와 사용하지 않을 때(Without-VGS)로 구분하여 에너지와 피사체 두께에 변화를 주고 흉부 팬텀과 대퇴부 팬텀을 이용하여 영상을 획득하고, SNR과 CNR을 분석하여 VGS의 유효성을 알아보고자 하였다. 흉부 팬텀과 대퇴부 팬텀에서 관전류는 2.5 mAs로 고정하고, 관전압을 60 ~ 100 kVp에서 10kVp 씩 변화하여 X선 조사한 후 SNR과 CNR을 측정한 결과 흉부 팬텀에서 SNR은 Without-VGS 보다 VGS에서 약 1.09 ~ 8.86% 높게 나타났고, CNR은 Without-VGS 보다 VGS에서 4.18 ~ 14.56% 높게 나타났다. 그리고 대퇴부 팬텀에서는 SNR이 Without-VGS 보다 VGS에서 약 9.78 ~ 18.05% 높게 나타났고, CNR은 Without-VGS 보다 VGS에서 21.07 ~ 44.44% 높게 나타났다. 흉부 팬텀과 대퇴부 팬텀에서 관전압을 70 kVp로 고정하고, 관전류량은 2.5 ~ 16 mAs에서 각각 변화하여 X선 조사한 후 SNR과 CNR을 측정한 결과 흉부 팬텀에서 SNR은 Without-VGS 보다 VGS에서 약 1.49 ~ 11.11% 높게 나타났고, CNR은 Without-VGS 보다 VGS에서 4.76 ~ 13.40% 높게 나타났다. 그리고 대퇴부 팬텀에서는 SNR은 Without-VGS 보다 VGS에서 약 2.22 ~ 17.38% 높게 나타났고, CNR은 Without-VGS 보다 VGS에서 13.85 ~ 40.46% 높게 나타났다. 결론적으로 Without-VGS 보다 VGS를 사용할 때 SNR과 CNR이 높게 나타났다. 그러므로 이동형 X선 촬영장치로 검사를 해야 하는 경우 이동형 그리드를 사용하기 어려운 환경에서 VGS를 사용함으로써 좋은 영상의 화질을 얻을 수 있어 검사에 유용하게 사용될 것으로 판단되고, 이동형 X선 장치의 활용성을 증대시킬 수 있을 것으로 판단된다.

• 한국추진공학회:학술대회논문집
• /
• 한국추진공학회 2008년 영문 학술대회
• /
• pp.157-159
• /
• 2008

An numerical investigation of the flow characteristics inside a diffusing S-duct inlet with and without vortex generators(VGs) was conducted. The primary discussion herein focuses on development of secondary flow in the S-duct with and without VGs, pressure recovery and distortion at the exit are also discussed. Full three-dimensional Navier-Stokes equations are solved using finite volume method and $k-\varepsilon$ turbulence model is employed. In order to validate the credibility of the numerical methods, predicted results of surface pressure are compared with flight test for the S-duct inlet without VGs, and it shows fairly good agreement. The result shows that VGs alter the flow characteristics in the S-duct and are effective in reducing distortion and ineffective in improving pressure recovery.

• 설비공학논문집
• /
• 제18권2호
• /
• pp.151-157
• /
• 2006

The present paper reports the method for evaluation of heat-transfer performance of finned tube heat exchangers in a low Reynolds number regime (Re = $160\~800$) and also reports the data of heat transfer and pressure loss taken from a finned tube heat exchanger with/without vortex generators (VGs) installed as a heat-transfer enhancement device. The evaluation is based on the modified single blow method conducted in a specially designed low Reynolds number duct. Three different test core geometries, i.e., fin only, fin-tube without VGs and that with VGs, are studied here. The data of heat transfer and pressure loss taken from the fin only geometry agree well with the empirical correlations, thus validating the present method as used for low Reynolds number regime. The data taken from the finned tube geometries with and without VGs are presented and compared to examine the effect of VGs in the low Reynolds number regime.

• 한국진공학회지
• /
• 제8권4B호
• /
• pp.536-540
• /
• 1999

We have developed a refractory WNx self-aligned gate GaAs metal-semiconductor field-effect transistor(MESFET) using $SiO_2$ side-wall process. The MESFET hasa fully ion-implanted, planar, symmetric self-alignment structure, and it is quite suitable for integration. The uniform trans-conductance of 354nS/mm up to Vgs=+0.6V and the saturation current of 171mA/mm were obtained. As high as 43GHz of cut-off frequency hs been realized without any de-embedding of parasitic effects. The refractory WNx self-aligned gate GaAs MESFET technology is one of the most promising candidates for realizing linear power amplifier ICs and multifunction monolithic ICs for use in the digital mobile communication systems such as hand-held phone(HHP), personal communication system (PCS) and wireless local loop(WLL).

• Journal of information and communication convergence engineering
• /
• 제10권1호
• /
• pp.85-90
• /
• 2012

A 40-MS/sec 10-bit pipelined analog to digital converter (ADC) with a 1.2 Vpp differential input signal is proposed. The implemented pipelined ADC consists of eight stages of 1.5 bit/stage, one stage of 2 bit/stage, a digital error correction block, band-gap reference circuit & reference driver, and clock generator. The 1.5 bit/stage consists of a sub-ADC, digital to analog (DAC), and gain stage, and the 2.0 bit/stage consists of only a 2-bit sub-ADC. A bootstrapped switch with a constant resistance is proposed to improve the linearity of the input switch. It reduces the maximum VGS variation of the conventional bootstrapped switch by 67%. The proposed bootstrapped switch is used in the first 1.5 bit/stage instead of a sample-hold amplifier (SHA). This results in the reduction of the hardware and power consumption. It also increases the input bandwidth and dynamic performance. A reference voltage for the ADC is driven by using an on-chip reference driver without an external reference. A digital error correction with a redundancy is also used to compensate for analog noise such as an input offset voltage of a comparator and a gain error of a gain stage. The proposed pipelined ADC is implemented by using a 0.18-${\mu}m$ 1- poly 5-metal CMOS process with a 1.8 V supply. The total area including a power decoupling capacitor and the power consumption are 0.95 $mm^2$ and 51.5 mW, respectively. The signal-to-noise and distortion ratio (SNDR) is 56.15 dB at the Nyquist frequency, resulting in an effective number of bits (ENOB) of 9.03 bits.