• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.11B
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• pp.1501-1509
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• 2001

Recently, the use of wireless communication systems has been rapidly increasing, which results in a difficult problem in efficient control of limited frequency resources. As a way of solving this problem, the ultra wideband time hopping impulse radio system attracts much attention. The impulse radio system communicates pulse position modulated data using Gaussian monocycle pulses of very short duration less than 1 nsec. Thus the transmitted signal has very low power spectral density and ultra wide bandwidth from near D.C. to a few GHz. It is blown that it hardly interferes with the existing communication systems because of its very low power spectral density. The purpose of this paper is to characterize multipath propagation of the impulse radio signal and to evaluate the performance of the correlator-based receiver for the multipath environments. In this paper, we consider the deterministic two-path model and the statistical indoor multipath model of Saleh and Valenzuela. For the two-path model the output of the correlator with the ideal reference waveform varies according to the relative difference between the indirect path delay and the time interval of PPM, and to the indirect path gains. In addition, the characteristics of bit error rates is measured for the two models through computer simulation. The simulation results indicate that the performance of the impulse radio system depends both on the relative difference between the indirect path delay and the time interval of PPM, and on the indirect path gains. Furthermore, it is observed that the reference signal designed for the AWGN channel can not be applied to the multipath channels.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.3
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• pp.46-55
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• 2016

This work proposes a 13b 100MS/s 45nm CMOS ADC with a high dynamic performance for IF-domain high-speed signal processing systems based on a four-step pipeline architecture to optimize operating specifications. The SHA employs a wideband high-speed sampling network properly to process high-frequency input signals exceeding a sampling frequency. The SHA and MDACs adopt a two-stage amplifier with a gain-boosting technique to obtain the required high DC gain and the wide signal-swing range, while the amplifier and bias circuits use the same unit-size devices repeatedly to minimize device mismatch. Furthermore, a separate analog power supply voltage for on-chip current and voltage references minimizes performance degradation caused by the undesired noise and interference from adjacent functional blocks during high-speed operation. The proposed ADC occupies an active die area of $0.70mm^2$, based on various process-insensitive layout techniques to minimize the physical process imperfection effects. The prototype ADC in a 45nm CMOS demonstrates a measured DNL and INL within 0.77LSB and 1.57LSB, with a maximum SNDR and SFDR of 64.2dB and 78.4dB at 100MS/s, respectively. The ADC is implemented with long-channel devices rather than minimum channel-length devices available in this CMOS technology to process a wide input range of $2.0V_{PP}$ for the required system and to obtain a high dynamic performance at IF-domain input signal bands. The ADC consumes 425.0mW with a single analog voltage of 2.5V and two digital voltages of 2.5V and 1.1V.