• Journal of the Korean Vacuum Society
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• v.9 no.1
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• pp.69-75
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• 2000

We have investigated the feasibility of spin on glass (SOG) film from polysilazane-type resin as a premetal dielectric (PMD) layer of the next-generation ultra-large scale integrated (ULSI) devices. A commercial polysilazane resin and a polysilazane-type resin with oxidizing agent were spin-coated and cured to form SOG films. In order to study the effect of oxidizing agent and annealing, the SOG films were characterized as cured and after annealing at $400^{\circ}C$ to $900^{\circ}C$. the density and the resistance against wet chemical of the SOG films were improved by the addition of oxidizing agent, because oxidizing agent enhanced the conversion from polysilazane polymer to $SiO_2$. The hole profile issue associated with insufficient curing of polysilazane in narrow gaps was also resolved by oxidizing agent, while the gapfill capability of SOG was not deteriorated by oxidizing agent.

• Journal of Korean Vacuum Science & Technology
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• v.2 no.2
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• pp.97-100
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• 1998

We have investigated the effects of crystalline activation on solid phase crystallization (SPC) of amorphous silicon (a-Si) thin films. Wet blasting and self ion implantation were employed as the activation treatments to induce macro or micro crystalline damages on deposited a-Si films. Low temperature and larger grain crystallization were obtained by the applied two-step activation. High degree of crystallinity was also observed on both furnace and rapid SPC. crystalline activations showed the promotion of nucleation on the activated regions and the retardation of growth in an amorphous matrix in SPC. The observed behavior of two-step SPC was strongly dependent on the applied activation and annealing processes. It was also found that the diversified effects by macro and micro activations on the SPC were virtually diminished as the annealing temperature increased.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.1
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• pp.41-47
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• 1992

In SFB Process, after 110$0^{\circ}C$ annealing in wet OS12T(95$^{\circ}C$ HS12TO bubbling) atmosphere, the existence of the interfacial oxide film in micro-gap at Si-Si bonding interface was identified. The angle lapping/staining and SEM morphologies of bonding interface showed that the growing behavior of interfacial oxide made a contribution to eliminate the micro-gaps having a width of 200-300$\AA$. In case of the diodes composed of p-n wafer pairs made by SFB processes, the annealed one in wet OS12T atmosphere exhibited a dielectric breakdown phenomena of interfacial oxide at 37-40 volts d.c.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.8 no.2
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• pp.299-306
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• 1998

Crystallization of the amorphous silicon needs activation. Thermal energy through laser annealing, furnace annealing and rapid thermal process (RTP) has been convinced to crystallize the amorphous silicon thin film. It is expected that some other type of energy like mechanical energy can help to crystallize the amorphous silicon thin film. In this study, mechanical energy through wet blasting of silica slurry and silicon ion implantation has been applied to the amorphous silicon thin film deposited with LPCVD technique. RTP was employed for the annealing of this mechanically-damaged amorphous silicon thin film. For the characterization of the crystallized silicon thin film, XRD and Raman analysis were conducted. In this study, it is shown that the mechanical damage is effective to enhance the crystallization of amorphous silicon thin film.

• Proceedings of the IEEK Conference
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• summer
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• pp.343-347
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• 2004

High oxidation temperature of SiC shows a tendency of carbide formation at the interface which results in poor MOSFET transfer characteristics. Thus we developed oxidation processes in order to get low interface charge densities. N-type 6H-SiC MOS capacitors were fabricated by different oxidation processes: dry, wet, and dry­reoxidation. Gate oxidation and Ar anneal temperature was $1150^{\circ}C.$ Ar annealing was performed after gate oxidation for 30 minutes. Dry-reoxidation condition was $950^{\circ}C,$ H2O ambient for 2 hours. Gate oxide thickness of dry, wet and dry-reoxidation samples were 38.0 nm, 38.7 nm, 38.5 nm, respectively. Mo was adopted for gate electrode. To investigate quality of these gate oxide films, high frequency C- V measurement, gate oxide leakage current, and interface trapped charge densities (Dit) were measured. The interface trapped charge densities (Dit) measured by conductance method was about $4\times10^{10}[cm^{-1}eV^{-1}]$ for dry and wet oxidation, the lowest ever reported, and $1\times10^{11}[cm^{-1}eV^{-1}]$ for dry-reoxidation

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.319-322
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• 1998

본 연구에서는 마스크의 폭을 각각 0.3.mu.m , 0.1.mu.m으로 설정하여 boron이 도핑된 실리콘 기판 위에 arsenic을 주입 시켰을때, 열처리 전과 각각 inert, dry, wet 산화분위기에서 열처리 한 후의 도핑 농도 프로파일과 수직 깊이와 측면으로의 퍼짐을 시뮬레이션하여 2차원적으로 관찰하였다. 마스크 폭을 축소시킴으로 인해 이온의 입사 방향으로 더 깊이 침투됨이 관찰되었으며, 더욱이 측면으로도 퍼짐이 관찰되었다. 열처리 전과 열처리 후의 비교에서도 농도프로파일이 보다 더 기판 내에서 넓게 분포됨이 관찰되었다.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.27 no.3
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• pp.143-147
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• 2017

To evaluate surface characteristics and improve crystalline quality of AlN single crystal grown by physical vapor transport (PVT) method, wet chemical etching process using $KOH/H_2O_2$ mixture in a low temperature condition and thermal annealing process was proceeded respectively. Conventional etching process using strong base etchant at a high temperature (above $300^{\circ}C$) had formed over etching phenomenon according to crystalline quality of materials. When it occurred to over etching phenomenon, it had a low reliability of dislocation density because it cannot show correct number of etch pits per estimated area. Therefore, it was proceeded to etching process in a low temperature (below $100^{\circ}C$) using $H_2O_2$ as an oxidizer in KOH aqueous solution and to be determined optimum etching condition and dislocation density via scanning electron microscope (SEM). For improving crystalline quality of AlN single crystal, thermal annealing process was proceeded. When compared with specimens as-prepared and as-annealed, full width at half maximum (FWHM) of the specimen as-annealed was decreased exponentially, and we analyzed the mechanism of this process via double crystal X-ray diffraction (DC-XRD).

• Progress in Superconductivity and Cryogenics
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• v.19 no.2
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• pp.25-28
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• 2017

In superconducting coil applications particularly in wet wound coils, coated conductor (CC) tapes are subjected to different type of stresses that could affect its electromechanical transport property. These include hoop stress acting along the length of the CC tape and the Lorentz force acting perpendicular to the CC tape's surface. Since the latter is commonly associated with the delamination problem of multi-layered REBCO CC tapes, more understanding and attention on the delamination phenomena induced in the case of coil applications are needed. Difference on the coefficient of thermal expansion (CTE) of each constituent layer of the CC tape, the bobbin, and the impregnating materials is the main causes of delamination in CC tapes when subjected to thermal and mechanical cycling. In the design of degradation-free superconducting coils, therefore, characterization of the delamination behaviors including mechanism and strength in the multi-layered REBCO CC tapes becomes a critical issue. Various trials to increase the delamination strength by improving interface characteristics at interlayers have been performed. In this study, in order to investigate the influences of laser cleaning and Ag annealing treated at the substrate side surface, transverse tensile tests were conducted under different sample configurations using $4.5mm{\times}8mm$ upper anvil. The mechanical delamination strength of differently processed CC samples was examined at room temperature (RT). As a result, the Sample 1 with the additional laser cleaning and Ag annealing processes and the Sample 2 with additional Ag annealing process only showed higher mechanical delamination strength as compared to the Sample 3 without such additional treatments. Sample 3 showed quite different behavior when the loading direction is to the substrate side where the delamination strength much lower as compared to other cases.

• Bulletin of the Korean Chemical Society
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• v.32 no.3
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• pp.1067-1070
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• 2011

We have demonstrated that solution-based fabrication of NiO films as HTL can be used for the construction of IOSCs. Type of solvent of NiO-solution, and annealing procedure of the active layers were optimized for obtaining a PCE of 3% of IOSC. The photovoltaic performance of NiO-based device is comparable to that of the same type of solar cell using PEDT:PSS instead of NiO. These solution-based processes can be a promising method for a mass production OSCs under ambient condition.

• Journal of the Korean institute of surface engineering
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• v.32 no.3
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• pp.389-392
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• 1999

We employed cobalt-disilicide for high-speed logic devices. We prepared stable and low resistant $CoSi_2$ through typical fabrication process including wet cleaning and rapid thermal process (RTP). We sputtered 15nm thick cobalt on the wafer and performed RTP annealing 2 times to obtain 60nm thick $CoSi_2$. We observed spherical shape voids with diameter of 40nm in the surface and inside $CoSi_2$ layers. The voids resulted in taking over abnormal junction leakage current and contact resistance values. We report that the voids in $CoSi_2$ layers are resulted from surface pits during the ion implantation previous to deposit cobalt layer. Silicide reaction rate around pits was enhanced due to Gibbs-Thompson effects and the volume expansion of the silicidation of the flat active regime trapped dimples. We confirmed that keeping the buffer oxide layer during ion implantation and annealing the silicon surface after ion implantation were required to prevent void defects in CoSi$_2$ layers.