• Journal of Korea Multimedia Society
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• v.18 no.6
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• pp.723-733
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• 2015

High availability is of utmost importance in real-time embedded systems. Temporary failures due to software or hardware faults should not result in a system crash. To achieve high availability, embedded systems typically use a combination of hardware and software techniques. A watchdog timer is a hardware component in embedded microprocessors that can be used to automatically reset the processor if software anomalies are detected. The embedded system relies on a single watchdog timer, however, can be permanently disabled if the timer is not properly configured, e.g. falling into an indefinite loop. STM32F4 provides two different types of watchdog timer in terms of timing accuracy and robustness. In this paper, we propose a hybrid approach, called long-tail watchdog timer, to utilize both timers to achieve self-reliance in embedded systems even though one of timers fails. Experimental results confirm that the proposed approach successfully handles various failure scenarios and present performance comparisons between single watchdog timer and hybrid approach in terms of configuration parameters of watchdog timers in STM32F4, counter value and window size.

• Proceedings of the Korean Information Science Society Conference
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• 2006.06a
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• pp.361-363
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• 2006

내장형 시스템은 우리들의 생활에 커다란 변화를 가져왔으며, 많은 적용분야와 다양한 기능을 갖추고 있어서 일상 생활에 널리 사용되고 있다. 문제는 이러한 기기들이 마이크로 컨트롤러에 가해지는 전기적 잡음과 전자기 방해가 많은 환경에서 사용되어지고 있다는 점이다. 따라서 이러한 환경에서는 시스템의 안정적인 운영을 도울 수 있는 기술중의 하나인 Watchdog Timer(WDT)가 필요하다. 본 논문에서는 WDT를 이용한 시스템 오류제어를 실시간 운영체제인 $UbiFOS^{TM}$에 적용하였다.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.9
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• pp.142-151
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• 1995

The trend of compact size, light weight, low power consumption in the portable telecommunication equipments demands large scale integration and low voltage operation of chips and the minimization of the number of the components in the telecommunication terminal. According to the trend, existing chip components are modulized and are integrated as a part into a bigger chip. This paper is about the development of the peripheral units of micro-controller for mobile telecommunication terminal. Peripherals consist of DMA controller, Interrupt controller, timer, watchdog timer, clock generator, and power management unit. They are designed to be integrated with EU(Execution Unit) and BIU(Bus Interface Unit) into a 16 bit micro-controller which will be used as a core of an ASIC for next generation digital mobile telecommunication terminal. At first, whole block of the micro-controller was described by VHDL behavioral model and simulated to verify its overall operation. Then, watchdog timer, clock generator and power management unit were directly synthesized by using VHDL synthesis tool. Rest of the pheriperal units were designed and simulated by using Compass Design Tool.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.603-604
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• 2008

This paper implemented The LED illuminance control IP based on 8bit RISC Processor. 8bit RISC Processor designed hardware interrupts, an interface for serial communications, a timer system with compare-capture-reload resources and a watchdog timer. LED Array consists of Red, Green, Blue, White and Warm White. The illuminance control IP is used to LED Board control with 8bit data.

• Journal of the Korea Society of Computer and Information
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• v.25 no.3
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• pp.89-96
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• 2020

Solar lamp systems may not operate normally in the event of some system or controller failure due to internal or external factors, in which case secondary problems occur, which may cost the system recovery. Thus, when these errors occur, a technology is needed to recover to the state it was in before the failure occurred and to enable re-execution. This paper designs and implements a system that can recover the state of the system to the state prior to the time of the error by using the Watchdog Timer within the controller if a software error has occurred inside the system, and it also proposes a technology to reset and re-execution the system through a separate reset circuit in the event of hardware failure. The proposed system provides stable operation, maintenance cost reduction and reliability of the solar lamp system by enabling the system to operate semi-permanently without external support by utilizing the automatic recovery and automatic reset function for errors that occur in the operation of the solar lamp system. In addition, it can be applied to maintain the system's constancy by utilizing the self-operation, diagnosis and recovery functions required in various high reliability applications.

• Proceedings of the Korea Information Processing Society Conference
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• 2005.11a
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• pp.1375-1378
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• 2005

향후 국내에서 개발되는 저궤도 관측위성의 고성능 탑재컴퓨터로 유럽에서 자체적으로 개발하여 위성용으로 활용하고 있는 MCM-ERC32 를 사용할 예정이다. MCM-ERC32 는 크게 32-비트 ERC32SC 프로세서와 프로세서의 기능을 보완하고 추가적인 기능들을 제공하기 위해 제작된 ASIC인 VASI(Very Advanced Sparc Interface), 그리고 메모리(SRAM, DRAM, EEPROM, etc.)로 구성되어 있다. 위성의 탑재소프트웨어를 설계 및 개발하는데 있어서 가장 기본적으로 요구되는 기능이 타이머이다. 탑재소프트웨어는 타이머를 통하여 태스크들의 관리와 스케쥴링 등을 수행하게 된다. 위성과 같이 높은 정확도가 요구되는 실시간 임베디드 시스템에서는 타이머의 구현이 매우 중요하다. ERC32SC 프로세서 자체에서도 RTC, GPT(General Purpose Timer), WDT(Watchdog Timer)와 같은 기본적인 타이머 기능을 제공하지만 VASI 에서도 클락과 사이클이라는 개념을 이용한 RTC 를 제공한다. 어느 타이머를 사용하는가는 전적으로 개발자의 선택이다. ERC32SC 프로세서에서 제공하는 타이머는 상용의 임베디드 시스템에서 제공하는 기능과 동일하다. 본 논문에서는 위성탑재소프트웨어 개발에 필요한 RTC 를 설계하기 위한 MCM-ERC32 에서 제공하는 VASI RTC 의 구조와 기능에 대하여 소개하고자 한다.

• Proceedings of the Korean Information Science Society Conference
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• 2000.10c
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• pp.219-221
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• 2000

최근 인터넷의 초고속 성장과 멀티미디어 데이터의 급격한 증가로 인해서, 고속의 전송매체와 이를 최적으로 이용하기 위한 인터페이스 시스템이 요구되고 있다. 이에 따라, 이더넷이 기가비트 이더넷으로 발전되어 LAN 인터페이스 시스템의 고속화를 이루고 있다. 그러나, 폭발적으로 증가하는 인터넷 환경에서 기가비트 이상의 고속 네트워크 대역폭을 지원하는 NIC(Network Interface Card)가 요구되고 있다. 이를 해결하고자, 기가비트 이상의 고속의 네트워크 대역폭을 지원하는 다중(Multiple) NIC의 연구가 진행되고 있다. 그러나, 고속의 네트워크 대역폭을 지원하는 다중 NIC를 운영할 때, 단일 NIC 결함으로 인해 시스템 운영이 중단되는 현상이 발생할 수 있다. 따라서, 효율적인 결함허용 기법을 적용하여 신뢰성 있는 시스템 운영을 지원할 필요성이 대두되고 있다. 본 논문에서는 기존의 하드웨어 결함 허용기법인 TMR, Primary-Standby Approach, Watchdog Timer 기법에서 발생되는 자원에 대한 가용성과 내구성의 비효율적인 부분을 고려하여, 동적으로 검출주기를 변환하여 다운타임(Downtime)을 최소화할 수 있는 효율적인 결함 허용 메카니즘을 설계하여 제안하고자 한다.

• Proceedings of the KOSOMBE Conference
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• v.1992 no.11
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• pp.83-85
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• 1992

In this paper, the Infant Incubator Consisting of amp lifer, A/D Convert, I/O Expand, Watchdog Timer, Alarm Circuit. Display, and mirco-Computer part was developed. The care of Premature new borns of the required that they be in an environment in which temperature is elevaled and Controlled, because they are unable to regulated their own temperature. The central and processing methods based on micro-processor employ the flexibility, and economy over other conventional system. The system characteristic were as follows 1) system based on micro-processor. 2) Easy-to read, touch-Operate control panel all displays and indicators 3) System flexibility.

• Journal of Internet Computing and Services
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• v.3 no.5
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• pp.31-39
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• 2002

A rapid growth of internet and sudden increase of multimedia data demands for high-speed transfer media and if optimizec usage from the interface system. To achieve this level of network bandwidth, multiple NICs for support of high-speed network bandwidth have been developed and studied. Furthermore, the use of multiple NICs can provide high-speed LAN environment without large network environment modification, supports backward compatibility of current system and reduce overhead. However. if system failure is caused by SPOF(Single Point of Failure) fault of large-capacity multiple NICs, incredible loss will be met because it services large capacity of multimedia data, Therefore, to prevent loss coming from faults, we describe 'Fault tolerance of multiple NICs', which use the fault prevention mechanism. Considering inefficiency of availability and serviceability that is occurred with existing TMR, Primary-Standby approach and Watchdog time mechanism, we propose and design the efficient fault tolerance mechanism, which minimize down time as changing of detection period dynamically. Consequently, the fault tolerance mechanism proposed for reducing overhead time when the fault is occurred, should minimize system downtime overall.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.34 no.2
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• pp.101-105
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• 2006

The Engineering Model of STSAT-2 on-board computer(OBC) was developed and tested completely with other sub-systems. The on-board computer of STSAT-2 has a high- performance PowerPC processors and a structure of centralized network communication. In addition, a lot of logics are implemented by Field Programmable Gate Array, such as interrupt controller, watchdog timer and UART. It could make the weight and size of OBC lighter and smaller. Also, the STSAT-2 on-board computer has more improved tolerance against Single Event Upsets and faults than that of the STSAT-1.