• Journal of the Semiconductor & Display Technology
• /
• v.3 no.3
• /
• pp.5-9
• /
• 2004

A new wafer level packaging scheme is presented as an alternative to MEMS package. The proof-of-concept structure is fabricated and evaluated to confirm the feasibility of the idea for MEMS wafer level packaging. The scheme of this work is developed using an electroplated tin (Sn) solder. The critical difference over conventional ones is that wafers are laterally bonded by solder reflow after LEGO-like assembly. This lateral bonding scheme has merits basically in morphological insensitivity and its better bonding strength over conventional ones and also enables not only the hermetic sealing but also its electrical interconnection solving an open-circuit problem by notching through via-hole. The bonding strength of the lateral bonding is over 30 Mpa as evaluated under shear and the hermeticity of the encapsulation is 2.0$\times10^{-9}$mbar.$l$/sec as examined by pressurized Helium leak rate. Results show that the new scheme is feasible and could be an alternative method for high yield wafer level packaging.

• Proceedings of the Korean Society of Precision Engineering Conference
• /
• 2010.05a
• /
• pp.509-510
• /
• 2010

• Proceedings of the International Microelectronics And Packaging Society Conference
• /
• 2000.10a
• /
• pp.177-193
• /
• 2000

• Proceedings of the International Microelectronics And Packaging Society Conference
• /
• 2003.09a
• /
• pp.165-172
• /
• 2003

Wafer-level packaging technology has become established with increase of demands for miniaturizing and realizing lightweight electronic devices evolution. This packaging technology enables the smallest footprint of packaged chip. Various structures and processes has been proposed and manufactured currently, and products taking advantages of wafer-level package come onto the market. The package enables mounting semiconductor chip on print circuit board as is a case with conventional die-level CSP's with BGA solder bumps. Bumping technology is also advancing in both lead-free solder alternative and wafer-level processing such as stencil printing using solder paste. It is known lead-free solder bump formation by stencil printing process tend to form voids in the re-flowed bump. From the result of FEM analysis, it has been found that the strain in solder joints with voids are not always larger than those of without voids. In this paper, characteristics of wafer-level package and effect of void in solder bump on its reliability will be discussed.

• Korean Journal of Materials Research
• /
• v.17 no.7
• /
• pp.347-351
• /
• 2007

Vertical interconnect technology called 3D stacking has been a major focus of the next generation of IC industries. 3D stacked devices in the vertical dimension give several important advantages over conventional two-dimensional scaling. The most eminent advantage is its performance improvement. Vertical device stacking enhances a performance such as inter-die bandwidth improvements, RC delay mitigation and geometrical routing and placement advantages. At present memory stacking options are of great interest to many industries and research institutes. However, these options are more focused on a form factor reduction rather than the high performance improvements. In order to improve a stacked device performance significantly vertical interconnect technology with wafer level stacking needs to be much more progressed with reduction in inter-wafer pitch and increases in the number of stacked layers. Even though 3D wafer level stacking technology offers many opportunities both in the short term and long term, the full performance benefits of 3D wafer level stacking require technological developments beyond simply the wafer stacking technology itself.

• Proceedings of the Korean Society of Precision Engineering Conference
• /
• 2013.05a
• /
• pp.509-510
• /
• 2013

• Journal of the Microelectronics and Packaging Society
• /
• v.25 no.1
• /
• pp.41-45
• /
• 2018

As the size of semiconductor chip shrinks, the electronic industry has been paying close attention to fan-out wafer level packaging (FO-WLP) as an emerging solution to accommodate high input and output density. FO-WLP also has several advantages, such as thin thickness and good thermal resistance, compared to conventional packaging technologies. However, one major challenge in current FO-WLP manufacturing process is to control wafer warpage, caused by the difference of coefficient of thermal expansion and Young's modulus among the materials. Wafer warpage induces misalignment of chips and interconnects, which eventually reduces product quality and reliability in high volume manufacturing. In order to control wafer warpage, it is necessary to understand the effect of material properties and design parameters, such as chip size, chip to mold ratio, and carrier thickness, during packaging processes. This paper focuses on the effects of thickness of chip and molding compound on 12" wafer warpage after PMC of EMC using finite element analysis. As a result, the largest warpage was observed at specific thickness ratio of chip and EMC.

• Journal of Sensor Science and Technology
• /
• v.27 no.5
• /
• pp.300-305
• /
• 2018

The uncooled microbolometer thermal sensor for low cost and mass volume was designed to target the new infrared market that includes smart device, automotive, energy management, and so on. The microbolometer sensor features 80x60 pixels low-resolution format and enables the use of wafer-level vacuum packaging (WLVP) technology. Read-out IC (ROIC) implements infrared signal detection and offset correction for fixed pattern noise (FPN) using an internal digital to analog convertor (DAC) value control function. A reliable WLVP thermal sensor was obtained with the design of lid wafer, the formation of Au80%wtSn20% eutectic solder, outgassing control and wafer to wafer bonding condition. The measurement of thermal conductance enables us to inspect the internal atmosphere condition of WLVP microbolometer sensor. The difference between the measurement value and design one is $3.6{\times}10-9$ [W/K] which indicates that thermal loss is mainly on account of floating legs. The mean time to failure (MTTF) of a WLVP thermal sensor is estimated to be about 10.2 years with a confidence level of 95 %. Reliability tests such as high temperature/low temperature, bump, vibration, etc. were also conducted. Devices were found to work properly after accelerated stress tests. A thermal camera with visible camera was developed. The thermal camera is available for non-contact temperature measurement providing an image that merged the thermal image and the visible image.

• Journal of the Korean Society of Manufacturing Technology Engineers
• /
• v.22 no.1
• /
• pp.168-172
• /
• 2013

In 3D wafer-stacking technology, one of the major issues is wafer warpage. Especially, The important reason of warpage has been known due to CTE(Coefficient of Thermal Expansion) mismatch between materials. It was too hard to choose how to make the FE model for blanket structured wafer level 3D packaging, because the thickness of each layer in wafer level 3D packaging was too small (micro meter or nano meter scale) comparing with diameter of wafer (6 or 8 inches). In this study, the FE model using the shell element was selected and simulated by the ANSYS WorkBench to investigate effects of the CTE on the warpage. To verify the FE model, it was compared by experimental results.

• Journal of the Microelectronics and Packaging Society
• /
• v.10 no.3
• /
• pp.57-65
• /
• 2003

In this study, we carry out reliability tests and investigate the failure mechanisms of the anodically bonded wafer level vacuum packaging (WLVP) MEMS gyroscope sensor. There are three failure mechanisms of WLVP: leakage, permeation and out-gassing. The leakage is caused by small dimension of the leak channel through the bonding interface and internal defects. The larger bonding width and the use of single crystalline silicon can reduce the leak rate. Silicon and glass wafer itself generates a large amount of outgassing including $H_2O$, $C_3H_5$, $CO_2$, and organic gases. Epi-poly wafer generates 10 times larger amount of outgassing than SOI wafer. The sandblasting process in the glass increases outgassing substantially. Outgassing can be minimized by pre-baking of the wafer in the vacuum oven before bonding process. An optimum pre-baking temperature of the wafers would be between $400^{\circ}C$ and $500^{\circ}C$.