• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.409-409
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• 2014

Recently hexagonal boron nitride (h-BN), III-V compound of boron and nitrogen with strong covalent $sp^2$ bond, is a 2 dimensional insulating material with a large direct band gap up to 6 eV. Its outstanding properties such as strong mechanical strength, high thermal conductivity, and chemical stability have been reported to be similar or superior to graphene. Because of these excellent properties, h-BN can potentially be used for variety of applications such as dielectric layer, deep UV optoelectronic device, and protective transparent substrate. Ultra flat and charge impurity-free surface of h-BN is also an ideal substrate to maintain electrical properties of 2 dimensional materials such as graphene. To synthesize a single or a few layered h-BN, chemical vapor deposition method (CVD) has been widely used by using an ammonia borane as a precursor. Ammonia borane decomposes into hydrogen (gas), monomeric aminoborane (solid), and borazine (gas) that is used for growing h-BN layer. However, very active monomeric aminoborane forms polymeric aminoborane nanoparticles that are white non-crystalline BN nanoparticles of 50~100 nm in diameter. The presence of these BN nanoparticles following the synthesis has been hampering the implementation of h-BN to various applications. Therefore, it is quite important to grow a clean and high quality h-BN layer free of BN particles without having to introduce complicated process steps. We have demonstrated a synthesis of a high quality h-BN monolayer free of BN nanoparticles in wafer-scale size of $7{\times}7cm^2$ by using CVD method incorporating a simple filter system. The measured results have shown that the filter can effectively remove BN nanoparticles by restricting them from reaching to Cu substrate. Layer thickness of about 0.48 nm measured by AFM, a Raman shift of $1,371{\sim}1,372cm^{-1}$ measured by micro Raman spectroscopy along with optical band gap of 6.06 eV estimated from UV-Vis Spectrophotometer confirm the formation of monolayer h-BN. Quantitative XPS analysis for the ratio of boron and nitrogen and CS-corrected HRTEM image of atomic resolution hexagonal lattices indicate a high quality stoichiometric h-BN. The method presented here provides a promising technique for the synthesis of high quality monolayer h-BN free of BN nanoparticles.

• Journal of the Korean Society for Nondestructive Testing
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• v.24 no.6
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• pp.573-580
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• 2004

The main goal of this study was to develop a micro-fabrication process for the capacitive micromachined ultrasonic transducer (cMUT). In order to achieve this goal, the former research results of the micro-electro-mechanical system (MEMS) process for the cMUT were analyzed. The membrane deposition, sacrificial layer deposition and etching were found to be a main process of fabricating the cMUT. The optimal conditions for those microfabrication were determined by the experiment. The thickness, uniformity, and residual stress of the $Si_3N_3$ deposition which forms the membrane of the cMUT were characterized after growing the $Si_3N_3$ on Si-wafer under various process conditions. As a sacrificial layer, the growth rate of the $SiO_2$ deposition was analyzed under several process conditions. The optimal etching conditions of the sacrificial layer were analyzed. The microfabrication process developed in this study will be used to fabricate the cMUT.

• Journal of the Korean Vacuum Society
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• v.7 no.1
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• pp.59-65
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• 1998

Multi-layer diamond-like carbon (DLC) films were deposited by 13.56 MHz r.f. PACVD method. Multi-layer DLC film was composed of 2.5 $mu extrm{m}$ thick pure DLC filml and 0.2$\mu\textrm{m}$ thick Si incorporated DLC (Si-DLC) film as a surface layer. Tribological behaviors of the multi-layer DLC film were investigated with a ball-on-disk type tribometer in ambient atmosphere using AISI 52100 steel ball. Low friction coefficient (<0.1) period increased with increasing the Si content in the surface Si-DLC film. The wear rate after 44,000 cycles and 158,400 cycles were the $2.5\times10^{-8}\sim1.8\times10^{-7}\textrm{mm}^3$/rev. and $7.1\times10^{-9}\sim1.8\times10^{-8}\textrm{mm}^3$/rev.,respectively. The wear rate of the multi-layer DLC film after 158,400 cycles was about 2 times smaller than that of pure DLC films of 2.7 $\mu\textrm{m}$ thickness. This high wear resistance and low friction coefficient was caused by the formation of Si oxide layer on the wear scar surface, as confirmed by the debris composition analysis. It was further shown that this si oxide debris layer on the wear scar surface is formed again even after removing the debris of the steel ball, which maintain the low friction coefficient between multi-layer DLC films and steel ball.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.204-205
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• 2011

In thin film silicon solar cells, p-i-n structure is adopted instead of p/n junction structure as in wafer-based Si solar cells. PECVD is a most widely used thin film deposition process for a-Si:H or ${\mu}c$-Si:H solar cells. For best performance of thin film silicon solar cell, the dopant profiles at p/i and i/n interfaces need to be as sharp as possible. The sharpness of dopant profiles can easily achieved when using multi-chamber PECVD equipment, in which each layer is deposited in separate chamber. However, in a single-chamber PECVD system, doped and intrinsic layers are deposited in one plasma chamber, which inevitably impedes sharp dopant profiles at the interfaces due to the contamination from previous deposition process. The cross-contamination between layers is a serious drawback of a single-chamber PECVD system in spite of the advantage of lower initial investment cost for the equipment. In order to resolve the cross-contamination problem in single-chamber PECVD systems, flushing method of the chamber with NH3 gas or water vapor after doped layer deposition process has been used. In this study, a new plasma process to solve the cross-contamination problem in a single-chamber PECVD system was suggested. A single-chamber VHF-PECVD system was used for superstrate type p-i-n a-Si:H solar cell manufacturing on Asahi-type U FTO glass. A 80 MHz and 20 watts of pulsed RF power was applied to the parallel plate RF cathode at the frequency of 10 kHz and 80% duty ratio. A mixture gas of Ar, H2 and SiH4 was used for i-layer deposition and the deposition pressure was 0.4 Torr. For p and n layer deposition, B2H6 and PH3 was used as doping gas, respectively. The deposition temperature was $250^{\circ}C$ and the total p-i-n layer thickness was about $3500{\AA}$. In order to remove the deposited B inside of the vacuum chamber during p-layer deposition, a high pulsed RF power of about 80 W was applied right after p-layer deposition without SiH4 gas, which is followed by i-layer and n-layer deposition. Finally, Ag was deposited as top electrode. The best initial solar cell efficiency of 9.5 % for test cell area of 0.2 $cm^2$ could be achieved by applying the in-situ plasma cleaning method. The dependence on RF power and treatment time was investigated along with the SIMS analysis of the p-i interface for boron profiles.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.20 no.1
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• pp.7-11
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• 2010

The reduction of optical losses in mono-crystalline silicon solar cell by surface texturing is a critical step to improve the overall cell efficiency. In this study, we have changed the sub-micrometer structure on the micrometer pyramidal structure by 2-step texturing. The Ag particles were coated on the micrometer pyramid surface in $AgNO_3$ solution, and then the etching with hydrogen fluoride and hydrogen peroxide created even smaller nano-pyramids in these pyramids. As a result, we observed that the changes of size and thickness of nano structure on pyramidal surface were determined by $AgNO_3$ concentration and etching time. Using 2-step texturing, the surface of wafers is etched to resemble the rough surface of a lotus leaf. Lotus surface can reduce average reflectance from 10% to below 3%. This reflectance is less than conventional textured wafer including anti-reflection coating.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.183-190
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• 2013

In this paper, we propose an improved anisotropic diffusion model for micro-crack detection in heterogeneously textured surface of polycrystalline solar wafers. Due to the nature of the image sensor, the gray-level of the diagonal micro-crack is non-uniform. Thus, the conventional algorithms can't fully detect diagonal micro-cracks when the number of iteration is not enough. However, the increasing of the iteration number leads to increase computation time and detects micro-crack thicker than the original micro-crack. In order to overcome this drawback, we use the gradient of north, south, east, and west directions as well as extended directions. To calculate the diffusion coefficients, we compare the gradients of conventional directions and extended directions and apply the larger gradient values to the coefficient function. This is because the proposed method reflects the information of diagonal micro-crack. Comparing to Tsai et al.'s and Ko and Rheem's, the proposed algorithm shows superior efficiency in detecting the diagonal micro-cracks with less iterations in the images of polycrystalline solar wafers. In addition, it also shows that the thickness of segmented micro-crack is similar to the orignal micro-crack.

• Composites Research
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• v.27 no.5
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• pp.183-189
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• 2014

Experimental considerations have been performed to obtain the clear optical microscopic images of graphene oxide which are useful to probe its quality and morphological information such as a shape, a size, and a thickness. In this study, we investigated the contrast enhancement of the optical images of graphene oxide after hydrazine vapor reduction on a Si substrate coated with a 300 nm-thick $SiO_2$ dielectric layer. Also, a green-filtered light source gave higher contrast images comparing to optical images under standard white light. Furthermore, it was found that a image channel separation technique can be an alternative to simply identify the morphological information of graphene oxide, where red, green, and blue color values are separated at each pixels of the optical image. The approaches performed in this study can be helpful to set up a simple and easy protocol for the morphological identification of graphene oxide using a conventional optical microscope instead of a scanning electron microscopy or an atomic force microscopy.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.477-477
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• 2008

For more than three decades, the gate dielectrics in CMOS devices are $SiO_2$ because of its blocking properties of current in insulated gate FET channels. As the dimensions of feature size have been scaled down (width and the thickness is reduced down to 50 urn and 2 urn or less), gate leakage current is increased and reliability of $SiO_2$ is reduced. Many metal oxides such as $TiO_2$, $Ta_2O_4$, $SrTiO_3$, $Al_2O_3$, $HfO_2$ and $ZrO_2$ have been challenged for memory devices. These materials posses relatively high dielectric constant, but $HfO_2$ and $Al_2O_3$ did not provide sufficient advantages over $SiO_2$ or $Si_3N_4$ because of reaction with Si substrate. Recently, $HfO_2$ have been attracted attention because Hf forms the most stable oxide with the highest heat of formation. In addition, Hf can reduce the native oxide layer by creating $HfO_2$. However, new gate oxide candidates must satisfy a standard CMOS process. In order to fabricate high density memories with small feature size, the plasma etch process should be developed by well understanding and optimizing plasma behaviors. Therefore, it is necessary that the etch behavior of $HfO_2$ and plasma parameters are systematically investigated as functions of process parameters including gas mixing ratio, rf power, pressure and temperature to determine the mechanism of plasma induced damage. However, there is few studies on the the etch mechanism and the surface reactions in $BCl_3$ based plasma to etch $HfO_2$ thin films. In this work, the samples of $HfO_2$ were prepared on Si wafer with using atomic layer deposition. In our previous work, the maximum etch rate of $BCl_3$/Ar were obtained 20% $BCl_3$/ 80% Ar. Over 20% $BCl_3$ addition, the etch rate of $HfO_2$ decreased. The etching rate of $HfO_2$ and selectivity of $HfO_2$ to Si were investigated with using in inductively coupled plasma etching system (ICP) and $BCl_3/Cl_2$/Ar plasma. The change of volume densities of radical and atoms were monitored with using optical emission spectroscopy analysis (OES). The variations of components of etched surfaces for $HfO_2$ was investigated with using x-ray photo electron spectroscopy (XPS). In order to investigate the accumulation of etch by products during etch process, the exposed surface of $HfO_2$ in $BCl_3/Cl_2$/Ar plasma was compared with surface of as-doped $HfO_2$ and all the surfaces of samples were examined with field emission scanning electron microscopy and atomic force microscope (AFM).

• Journal of Sensor Science and Technology
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• v.6 no.5
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• pp.346-355
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• 1997

In this paper, the analyses of the stress disturibution and frequency characteristics of silicon microstructures for an accelerometer were performed using the general purpose finite element simulation program, ANSYS. From the analyses, we determined the parameter values of a new 6-beam piezoresistive accelerometer applicable to the accelerometer's specification in airbag system of automobile. Then, the mass paddle radius, beam length, beam width, and beam thickness of the designed accelerometer were$500{\mu}m$, $350{\mu}m$, $100{\mu}m$, and $5{\mu}m$, respectively and two different seismic masses with 0.4 mg and 0.8 mg were defined on the same sensor structure. The designed 6- beam accelerometers were fabricated on the selectively diffused (111)-oriented $n/n^{+}/n$ silicon substrates and the characteristics of the fabricated accelerometers were investigated. Then, we used a micromachining technique using porous silicon etching method for the formation of the micromechanical structure of the accelerometer.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.155.2-155.2
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• 2013

Strain-relaxed SiGe layer on Si substrate has numerous potential applications for electronic and opto- electronic devices. SiGe layer must have a high degree of strain relaxation and a low dislocation density. Conventionally, strain-relaxed SiGe on Si has been manufactured using compositionally graded buffers, in which very thick SiGe buffers of several micrometers are grown on a Si substrate with Ge composition increasing from the Si substrate to the surface. In this study, a new plasma process, i.e., the combination of PIII&D and HiPIMS, was adopted to implant Ge ions into Si wafer for direct formation of SiGe layer on Si substrate. Due to the high peak power density applied the Ge sputtering target during HiPIMS operation, a large fraction of sputtered Ge atoms is ionized. If the negative high voltage pulse applied to the sample stage in PIII&D system is synchronized with the pulsed Ge plasma, the ion implantation of Ge ions can be successfully accomplished. The PIII&D system for Ge ion implantation on Si (100) substrate was equipped with 3'-magnetron sputtering guns with Ge and Si target, which were operated with a HiPIMS pulsed-DC power supply. The sample stage with Si substrate was pulse-biased using a separate hard-tube pulser. During the implantation operation, HiPIMS pulse and substrate's negative bias pulse were synchronized at the same frequency of 50 Hz. The pulse voltage applied to the Ge sputtering target was -1200 V and the pulse width was 80 usec. While operating the Ge sputtering gun in HiPIMS mode, a pulse bias of -50 kV was applied to the Si substrate. The pulse width was 50 usec with a 30 usec delay time with respect to the HiPIMS pulse. Ge ion implantation process was performed for 30 min. to achieve approximately 20 % of Ge concentration in Si substrate. Right after Ge ion implantation, ~50 nm thick Si capping layer was deposited to prevent oxidation during subsequent RTA process at $1000^{\circ}C$ in N2 environment. The Ge-implanted Si samples were analyzed using Auger electron spectroscopy, High-resolution X-ray diffractometer, Raman spectroscopy, and Transmission electron microscopy to investigate the depth distribution, the degree of strain relaxation, and the crystalline structure, respectively. The analysis results showed that a strain-relaxed SiGe layer of ~100 nm thickness could be effectively formed on Si substrate by direct Ge ion implantation using the newly-developed PIII&D process for non-gaseous elements.