• 제목/요약/키워드: Wafer thickness

검색결과 465건 처리시간 0.024초

구리 박막 CMP의 실시간 end point detection을 위한 데이터 정밀도 개선 방법에 관한 연구 (A Study of Data correction method when in-situ end point detection in Chemical-Mechanical Polishing of Copper Overlay)

  • 김남우;허창우
    • 한국정보통신학회논문지
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    • 제18권6호
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    • pp.1401-1406
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    • 2014
  • 반도체소자의 제조 공정 기술 중 구리패턴을 얻기 위해서 사용하는 화학 기계적 연마(CMP)를 이용한 평탄화와 연마 공정에서 Wafer에 도포된 구리의 두께를 실시간으로 측정하여 정밀하게 제어할필요가 있는데, 이때 획득되는 센서값을 실제 두께 값으로 환산하는 계산과정에서 오차가 발생할 수 있다. 실제 측정 값에 근사한 값을 얻도록 단순평균을 이용한 방법, 이동 평균, 필터 들을 사용하여 결과를 비교하여 옹고스트롬 단위의 두께를 실시간으로 측정하는 제어 시스템의 편차를 줄이도록 하는 방법의 구현에 대해 기술한다.

유한요소해석을 이용한 백그라인딩 장비의 구조안정성 연구 (A study on structural stability of Backgrinding equipment using finite element analysis)

  • 위은찬;고민성;김현정;김성철;이주형;백승엽
    • Design & Manufacturing
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    • 제14권4호
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    • pp.58-64
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    • 2020
  • Lately, the development of the semiconductor industry has led to the miniaturization of electronic devices. Therefore, semiconductor wafers of very thin thickness that can be used in Multi-Chip Packages are required. There is active research on the backgrinding process to reduce the thickness of the wafer. The backgrinding process polishes the backside of the wafer, reducing the thickness of the wafer to tens of ㎛. The equipment that performs the backgrinding process requires ultra-precision. Currently, there is no full auto backgrinding equipment in Korea. Therefore, in this study, ultra-precision backgrinding equipment was designed. In addition, finite element analysis was conducted to verify the equipment design validity. The deflection and structural stability of the backgrinding equipment were analyzed using finite element analysis.

반도체 3차원 칩 적층을 위한 미세 범프 조이닝 기술 (Micro-bump Joining Technology for 3 Dimensional Chip Stacking)

  • 고영기;고용호;이창우
    • 한국정밀공학회지
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    • 제31권10호
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    • pp.865-871
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    • 2014
  • Paradigm shift to 3-D chip stacking in electronic packaging has induced a lot of integration challenges due to the reduction in wafer thickness and pitch size. This study presents a hybrid bonding technology by self-alignment effect in order to improve the flip chip bonding accuracy with ultra-thin wafer. Optimization of Cu pillar bump formation and evaluation of various factors on self-alignment effect was performed. As a result, highly-improved bonding accuracy of thin wafer with a $50{\mu}m$ of thickness was achieved without solder bridging or bump misalignment by applying reflow process after thermo-compression bonding process. Reflow process caused the inherently-misaligned micro-bump to be aligned due to the interface tension between Si die and solder bump. Control of solder bump volume with respect to the chip dimension was the critical factor for self-alignment effect. This study indicated that bump design for 3D packaging could be tuned for the improvement of micro-bonding quality.

매엽식 방법을 이용한 웨이퍼 후면의 박막 식각 (Etching Method of Thin Film on the Backside of Wafer Using Single Wafer Processing Tool)

  • 안영기;김현종;구교욱;조중근
    • 반도체디스플레이기술학회지
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    • 제5권2호
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    • pp.47-49
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    • 2006
  • Various methods of making thin film is being used in semiconductor manufacturing process. The most common method in this field includes CVD(Chemical Vapor Deposition) and PVD(Physical Vapor Deposition). Thin film is deposited on both the backside and the frontside of wafers. The thin film deposited on the backside has poor thickness profile, and can contaminate wafers in the following processes. If wafers with the thin film remaining on the backside are immersed in batch type process tank, the thin film fall apart from the backside and contaminate the nearest wafer. Thus, it is necessary to etch the backside of the wafer selectively without etching the frontside, and chemical injection nozzle positioned under the wafer can perform the backside etching. In this study, the backside chemical injection nozzle with optimized chemical injection profile is built for single wafer tool. The evaluation of this nozzle, performed on $Si_3N_4$ layer deposited on the backside of the wafer, shows the etching rate uniformity of less than 5% at the etching rate of more than $1000{\AA}$.

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실리콘 웨이퍼의 고정밀 단면 연삭에 관한 연구 (A Study on Precision Infeed Grinding for the Silicon Wafer)

  • 안대균;황징연;최성주;곽창용;하상백
    • 한국정밀공학회:학술대회논문집
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    • 한국정밀공학회 2005년도 춘계학술대회 논문집
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    • pp.1-5
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    • 2005
  • The grinding process is replacing lapping and etching process because significant cost savings and performance improvemnets is possible. This paper presents the experimental results of wafer grinding. A three-variable two-level full factorial design was employed to reveal the main effects as well as the interaction effects of three process parameters such as wheel rotational speed, chuck table rotational speed and feed rate on TTV and STIR of wafers. The chuck table rotaional speed was a significant factor and the interaction effects was significant. The ground wafer shape was affected by surface shape of chuck table.

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본딩 웨이퍼 분석 시스템 개발 (Development of Bonded Wafer Analysis System)

  • 장동영;반창우;임영환;홍석기
    • 대한기계학회논문집A
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    • 제33권9호
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    • pp.969-975
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    • 2009
  • In this paper, bonded wafer analysis system is proposed using laser beam transmission; while the transmission model is derived by simulation. Since the failure of bonded wafer stems in void existence, transmittance deviations caused by the thickness of the void are analyzed and variations of the intensity through the void or defect easily have been recognized then the testing power has been increased. In addition, large screen display on laser study has been done which resulted in acquiring a feasible technique for analysis of the whole bonding surface. In this regard, three approaches are demonstrated in which Halogen lamp, IR lamp and laser have been tested and subsequently by results comparison the optimized technique using laser has been derived.

SOI(Silicon-On-Insulator)- Micromachining 기술을 이용한 MEMS 소자의 제작 (Fabrication of MEMS Devices Using SOI(Silicon-On-Insulator)-Micromachining Technology)

  • 주병권;하주환;서상원;최승우;최우범
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2001년도 하계학술대회 논문집
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    • pp.874-877
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    • 2001
  • SOI(Silicon-On-Insulator) technology is proposed as an alternative to bulk silicon for MEMS(Micro Electro Mechanical System) manufacturing. In this paper, we fabricated the SOI wafer with uniform active layer thickness by silicon direct bonding and mechanical polishing processes. Specially-designed electrostatic bonding system is introduced which is available for vacuum packaging and silicon-glass wafer bonding for SOG(Silicon On Glass) wafer. We demonstrated thermopile sensor and RF resonator using the SOI wafer, which has the merits of simple process and uniform membrane fabrication.

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Characteristics of Electrowetting of Self-assembled Monolayer and Z-Tetraol Film

  • Lin Li-Yu;Noh Dong-Sun;Kim Dae-Eun
    • International Journal of Precision Engineering and Manufacturing
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    • 제7권3호
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    • pp.35-38
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    • 2006
  • A study of electrowetting using an Octadecyltrichlorosilane (OTS) self-assembled monolayer (SAM) and Z- Tetraol 2000 perfluoropolyether lubricant as hydrophobic layers on Si and $SiO_2$ wafer was performed. The $SiO_2$ layer used as insulating layer was thermally grown on the silicon wafer to a thickness of 220-230 nm. The results demonstrated that the contact angle decreased from $100^{\circ}$ to $80^{\circ}$ at 28 V applied potential on $SiO_2$ wafer coated with OTS and the contact angle appeared to be reversible. However, the contact angle on the $SiO_2$ wafer coated with Z- Tetraol 2000 was not observable at 28 V applied potential. Furthermore, the contact angle on the Si wafer coated with OTS or Z- Tetraol 2000 appeared to be irreversible due to the generation of electrolysis in the droplet. It is concluded that it is feasible to use SAM as a hydrophobic layer in electrowetting applications.

볼브레이커시험에 의한 실리콘 다이의 표면조건에 따른 파단강도 평가 (Evaluation of Fracture Strength of Silicon Die with Surface Condition by Ball Breaker Test)

  • 변재원
    • 열처리공학회지
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    • 제26권4호
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    • pp.178-184
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    • 2013
  • The effects of thickness and surface grinding condition on the fracture strength of Si wafer with a thickness under $100{\mu}m$ were investigated. Fracture strength was measured by ball breaker test for about 330 dies (size: $4mm{\times}4mm$) per each wafer. For statistical analysis of the fracture strength, scale factor was determined from Weibull plot. Ball breaker fracture strength was observed to increase with decreasing thickness of silicon die. For the silicon dies of different surface conditions, ball breaker fracture strength was high in the order of polished, ground (#4800), and ground (#320 grit) specimen. Probabilistic fracture strength (i.e., scale factor) increased with decreasing surface roughness of silicon die.

Wafer Spin Coating 공정에서 증발과 용액이 박막 형성에 미치는 영향에 관한 연구 (A Numerical Study on Combined Solution and Evaporation during Spin Coating Process)

  • 노영미;임익태;김광선
    • 반도체디스플레이기술학회지
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    • 제2권1호
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    • pp.25-29
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    • 2003
  • The fluid flow, mass transfer, heat transfer and film thickness variation during the spin coating process are numerically studied. The model is said to be I-dimensional because radial variations in film thickness, concentration and temperature are ignored. The finite difference method is employed to solve the equations that are simplified using the similarity transformation. In early time, the film thinning is due to the radial convective outflow. However that slows during the first seconds of spinning so the film thinning due to evaporation of solvent becomes sole. The time varing film thickness is analyzed according to the wafer spin speed, the various solvent fraction in the coating liquid, and the various solvent vapor fraction in the bulk of the overlying gas during the spin coating is estimated.

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