• 대한전자공학회논문지SD
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• 제44권1호
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• pp.22-27
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• 2007

반도체 또는 평판디스플레이 제조에 있어 노광공정 후의 PR(photoresist) 제거 공정으로 이용하기 위하여 경계 막 제어에 의한 오존처리공정 및 설비 구현에 대한 연구를 수행하였다. 개발한 초 고농도 오존생성기술과 vapor 발생 방식 경계 막 제어 오존처리공정설비에 의해 실리콘 웨이퍼 PR 제거시험을 수행하였으며 오존가스농도 16wt%, 오존가스 유량 $8[\ell/min]$에서 약 400nm/분의 높은 PR 제거율을 달성하였다.

• 마이크로전자및패키징학회지
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• 제19권4호
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• pp.45-50
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• 2012

A family of multi-die DRAM packages was developed that incorporate the full functionality of an SODIMM into a single package. Using a common ball assignment analogous to the edge connector of an SODIMM, a broad range of memory types and assembly structures are supported in this new package. In particular DDR3U, LPDDR3 and DDR4RS are all supported. The center-bonded DRAM use face-down wirebond assembly, while the peripherybonded LPDDR3 use the face-up configuration. Flip chip assembly as well as TSV stacked memory is also supported in this new technology. For the center-bonded devices (DDR3, DDR4 and LPDDR3 ${\times}16$ die) and for the face up wirebonded ${\times}32$ LPDDR3 devices, a simple manufacturing flow is used: all die are placed on the strip in a single machine insertion and are sourced from a single wafer. Wirebonding is also a single insertion operation: all die on a strip are wirebonded at the same time. Because the locations of the power signals is unchanged for these different types of memories, a single consolidated set of test hardware can be used for testing and burn-in for all three memory types.

• 한국결정학회지
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• 제12권2호
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• pp.102-112
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• 2001

단결정 실리콘의 기계적 손상거동에 대한 이해는 반도체 정밀가공의 관점에서 매우 중요하다. 최근 이루어지고 있는 Diamond Anvil Cell(DAC) 이나 압입시험을 통한 고압상연구로 부터 실리콘은 고압에서 일련의 상변화과정을 겪는다는 것이 알려지고 있으며 마찬가지로 실리콘에 다이아몬드 팁으로 scratching시험을 하는 과정에서 다양한 기계적인 손상과 응력상들이 나타날 수 있다. 본 연구에서는 단결정 실리콘에 대하여 scratching시험에 의하여 나 타나는 균열에 대하여 고찰하고 mirco-Raman 분광법을 사용하여 scratching에 의하여 나타나는 상을 분석하였다. 그 결과 scratching 방향과 속도에 따라 균열의 양상이 달라지며 scratching속도와 하중조건에 따라 여러가지 다른 상이 관찰됨을 확인하였다

• 한국군사과학기술학회지
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• 제12권4호
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• pp.446-451
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• 2009

In this paper, we described the design and test results of a high output power amplifier MMIC developed by using 0.5um power pHEMT processes on a 6-inch GaAs wafer for the X-band T/R module application. In the MMIC design, we have used a simple on-chip gate active bias technology to compensate the threshold-voltage variation of pHEMT during the fabrication process and 16-to-1 power combining method to achieve the output power over 10watt. The fabricated chip has an output power over 12watts and maximum PAE of 32% over the frequency range of fo +/-750MHz.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2003년도 춘계학술대회
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• pp.25-30
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• 2003

The total relaxed stress in annealing and the thermal strain/stress were obtained from the identification of the residual stress-free state using electronic speckle pattern interferometry (ESPI). The residual stress fields in case of both single and film/substrate systems were modeled using the thermo-elastic theory and the relationship between relaxed stresses and displacements. We mapped the surface residual stress fields on the indented bulk Cu and the 0.5 ${\mu}m$ Au film by ESPI. In indented Cu, the normal and shear residual stress are distributed over -1.7 GPa to 700 MPa and -800 GPa to 600 MPa respectively around the indented point and in deposited Au film on Si wafer, the tensile residual stress is uniformly distributed on the Au film from 500 MPa to 800 MPa. Also we measured the residual stress by the x-ray diffractometer (XRD) for the verification of above residual stress results by ESPI.

• Tribology and Lubricants
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• 제11권5호
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• pp.59-65
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• 1995

Tribological behaviors of nitrogen incorporated amorphous diamond-like carbon films were experimentally measured under a vacuum ($3 \times 10^{-5}$ Torr) using a ball (AISI 52100 steel)-on-disk wear-rig. Nitrogen incorporated DLC films were deposited by r.f. plasma assisted chemical vapor deposition method. Mixtures of benzene and ammonia or nitrogen gases were used as the reaction gases for the r.f. PACVD, and Si (100) wafer was used as the substrate. In the tribo-test, effects of DLC film thickness and normal load in friction were measured and discussed. Results showed that friction of nitrogen incorporated DLC films from a mixture gas of benzene and ammonia was lower than that of 100% benzene, specially in the measurement of minimum coefficient of friction. Differences in frictional characteristics of nitrogen incorporated DLC films were explained with the changes in chemical structures of the films. Result also showed that friction of DLC films increased with the sliding contact cycle, which remarkably accompanied with roll-shaped wear debris. Mechanisms and roles of the polymer-like wear debris were presented and discussed.

• 연구논문집
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• 통권33호
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• pp.99-109
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• 2003

Recently the utilization of the ozone dissolved de-ionized water(DIW-$O_3$) in semiconductor wet cleaning process and photoresist stripping process to replace the conventional sulfuric acid and hydro peroxide mixture(SPM) method has been studied. In this paper, we propose the water-electrode type ozone generator which has the characteristics of the high concentration and purity to produce the high concentration DIW-$O_3$ for the photoresist strip process in the semiconductor fabrication. The proposed ozone generator has the dual dielectric tube structure of silent discharge type and the water is both used to electrode and cooling water. Through this study, we obtained the results of the 10.3 wt% of ozone gas concentration at the oxygen gas of 0.5 [liter/min.] and the DIW-$O_3$ concentration of 79.5 ppm.. Through the photoresist stripping test using the produced DIW-$O_3$, we confirmed that the photoresist coated on the silicon wafer was removed effectively in the 12 minutes.

• 소성∙가공
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• 제13권8호
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• pp.716-722
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• 2004

Effects of sliding speed, applied load, and thickness of PMMA (Poly Methyl Methacrylate) coating layers on their dry sliding frictional and wear behavior were investigated. Sliding wear tests were carried out using a pin-on-disk wear tester. The PMMA layer was coated on Si wafer by a spin coating process with two different thicknesses, $1.5\mu\textrm{m}$ and $0.8\mu\textrm{m}$. AISI 52100 bearing steel balls were used as a counterpart of the PMMA coating during the wear. Normal applied load and sliding speed were varied. Wear mechanisms of the coatings were investigated by examining worn surfaces using an SEM. Friction coefficient of the coatings decreased with the increase of the applied load. Both adhesion and deformation of the coating determined the coefficient. The thicker PMMA layer with the thickness of $1.5mutextrm{m}$ showed lower friction coefficient than the thinner layer under most test conditions. Effects of sliding speed and applied load on the frictional behavior were varied depending on the thickness of the coating layer.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권1호
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• pp.22-27
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• 2013

Detailed study on how the plasma process during the sidewall spacer formation suppresses the formation of silicide is done. In non-patterned wafer test, it is found that both fluorocarbon reactive ion etch (RIE) and TEOS plasma-enhanced deposition processes modify the Si surface so that the silicide reaction is chemically inhibited or suppressed. In order to investigate the cause of the chemical modification, we analyze the elements on the silicon surface through Auger Electron Spectroscopy (AES). From the AES result, it is found that the carbon induces chemical modification which blocks the reaction between silicon and nickel. Thus, protecting the surface from the carbon-containing plasma process prior to nickel deposition appears critical in successful silicide formation.

• Transactions on Electrical and Electronic Materials
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• 제2권3호
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• pp.24-27
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• 2001

The end point of oxide chemical mechanical polishing (CMP) have determined by polishing time calculated from removal rate and target thickness of oxide. This study is about control of oxide removal amounts on the shallow trench isolation (STI) patterned wafers using removal rate and thickness of blanket (non-patterned) wafers. At first, it was investigated the removal properties of PETEOS blanket wafers, and then it was compared with the removal properties and the planarization (step height) as a function of polishing time of the specific STI patterned wafers. We found that there is a relationship between the oxide removal amounts of blanket and patterned wafers. We analyzed this relationship, and the post CMP thickness of patterned wafers could be controlled by removal rate and removal target thickness of blanket wafers. As the result of correlation analysis, we confirmed that there was the strong correlation between patterned and blanket wafer (correlation factor: 0.7109). So, we could confirm the repeatability as applying for STI CMP process from the obtained linear formula. As the result of repeatability test, the differences of calculated polishing time and actual polishing time was about 3.48 seconds. If this time is converted into the thickness, then it is from 104 $\AA$ to 167 $\AA$. It is possible to be ignored because process margin is about 1800 $\AA$.