• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.12S
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• pp.1237-1241
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• 2003

In this paper, we report a novel RF-MEMS packaging technology with lightweight, small size, and short electric path length. To achieve this goal, we used the ultra thin silicon substrate as a packaging substrate. The via holes lot vortical feed-through were fabricated on the thin silicon wafer by wet chemical processing. Then, via holes were filled and micro-bumps were fabricated by electroplating. The packaged RF device has a reflection loss under 22 〔㏈〕 and a insertion loss of -0.04∼-0.08 〔㏈〕. These measurements show that we could package the RF device without loss and interference by using the vertical feed-through. Specially, with the ultra thin silicon wafer we can realize of a device package that has low-cost, lightweight and small size. Also, we can extend a 3-D packaging structure by stacking assembled thin packages.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.09a
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• pp.165-172
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• 2003

Wafer-level packaging technology has become established with increase of demands for miniaturizing and realizing lightweight electronic devices evolution. This packaging technology enables the smallest footprint of packaged chip. Various structures and processes has been proposed and manufactured currently, and products taking advantages of wafer-level package come onto the market. The package enables mounting semiconductor chip on print circuit board as is a case with conventional die-level CSP's with BGA solder bumps. Bumping technology is also advancing in both lead-free solder alternative and wafer-level processing such as stencil printing using solder paste. It is known lead-free solder bump formation by stencil printing process tend to form voids in the re-flowed bump. From the result of FEM analysis, it has been found that the strain in solder joints with voids are not always larger than those of without voids. In this paper, characteristics of wafer-level package and effect of void in solder bump on its reliability will be discussed.

• Electronics and Telecommunications Trends
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• v.36 no.3
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• pp.23-33
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• 2021

Two main technologies of III-V/Si laser diode for optical communication, direct epitaxial growth, and wafer bonding were studied. Until now, the wafer bonding has been vigorously studied and seems promising for the ideal III-V/Si laser. However, the wafer bonding process is still complicated and has a limit of mass production. The development of a concise and innovative integration method for silicon photonics is urgent. In the future, the demand for high-speed data processing and energy saving, as well as ultra-high density integration, will increase. Therefore, the study for the hetero-junction, which is that the III-V compound semiconductor is directly grown on Si semiconductor can overcome the current limitations and may be the goal for the ideal III-V/Si laser diode.

• 제어로봇시스템학회:학술대회논문집
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• 1995.10a
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• pp.79-82
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• 1995

The problem of temperature control for rapid thermal processing (RTP) in semiconductor manufacturing is discussed in this paper. Among sub=micron technologies for VLSI devices, reducing the junction depth of doped region is of great importance. This paper investigates existing methods for manufacturing wafers, focusing on the RPT which is considered to be good for formation of shallow junctions and performs the wafer fabrication operation in a single chamber of annealing, oxidation, chemical vapor deposition, etc., within a few minutes. In RTP for semiconductor manufacturing, accurate and uniform control of the wafer temperature is essential. In this paper, a robustr controller is designed using a recently developed optimization technique. The controller designed is then tested via computer simulation and compared with the other results.

• Journal of the Semiconductor & Display Technology
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• v.1 no.1
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• pp.9-13
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• 2002

A polyimide-type electrostatic chuck (ESC) was fabricated for the application of holding 8-inch silicon wafers in the oxide etching equipment. For the fabrication of the unipolar ESC, core technologies such as coating of polyimide films and anodizing treatment of aluminum surface were developed. The polyimide films were prepared on top of thin coated copper substrates for the good electrical contacts, and the helium gas cooling technique was used for the temperature uniformity of the silicon wafers. The ESC was essentially working with an unipolar operation, which was easier to fabricate and operate compared to a bipolar operation. The chucking force of the ESC has been measured to be about 580 gf when the applied voltage was 1.5 kV, which was considered to be enough force to hold wafers during the dry etching processing. The employment of the ESC in etcher system could make 8% enhancement of the wafer processing yield.

• Laser Solutions
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• v.9 no.3
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• pp.7-13
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• 2006

Auto focusing system to find optimized focal position of laser beam used for material process has been investigated by using fiber confocal method. Wavelength of laser diode (LD) and diameter of single-mode fiber are 780nm and $5.3{\mu}m$, respectively. Intensity distributions of beam reflected from the surface of mirror and silicon bare wafer have been observed in a gaussian form. Experimental results show that focal position obtained by LD is shifted from one observed from surface scribed by laser about $80{\mu}m$. It is due to the difference of wavelength and each divergence of between LD and laser used for material process. It is confirmed that auto focusing control system through position calibration has operated steadily.

• Journal of Institute of Control, Robotics and Systems
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• v.6 no.1
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• pp.104-111
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• 2000

A fuzzy logic Run-by-Run(RbR) controller and an in -line wafer characteristics prediction scheme for the rapid thermal processing system have been developed for the study of process repeatability. The fuzzy logic RbR controller provides a framework for controlling a process which is subject to disturbances such as shifts and drifts as a normal part of its operation. The fuzzy logic RbR controller combines the advantages of both fuzzy logic and feedback control. It has two components : fuzzy logic diagnostic system and model modification system. At first, a neural network model is constructed with the I/O data collected during the designed experiments. The wafer state after each run is assessed by the fuzzy logic diagnostic system with featuring step. The model modification system updates the existing neural network process model in case of process shift or drift, and then select a new recipe based on the updated model using genetic algorithm. After this procedure, wafer characteristics are predicted from the in-line wafer characteristics prediction model with principal component analysis. The fuzzy logic RbR controller has been applied to the control of Titanium SALICIDE process. After completing all of the above, it follows that: 1) the fuzzy logic RbR controller can compensate the process draft, and 2) the in-line wafer characteristics prediction scheme can reduce the measurement cost and time.

• Journal of the Semiconductor & Display Technology
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• v.22 no.4
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• pp.108-112
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• 2023

Precision manufacturing technology is rapidly developing due to the extreme miniaturization of semiconductor processes to comply with Moore's Law. Accurate and precise alignment, which is one of the key elements of the semiconductor pre-process and post-process, is very important in the semiconductor process. The center detection of wafer align marks plays a key role in improving yield by reducing defects and research on accurate detection methods for this is necessary. Methods for accurate alignment using traditional image sensors can cause problems due to changes in image brightness and noise. To solve this problem, engineers must go directly into the line and perform maintenance work. This paper emphasizes that the development of AI technology can provide innovative solutions in the semiconductor process as high-resolution image and image processing technology also develops. This study proposes a new wafer center detection method through variable thresholding. And this study introduces a method for detecting the center that is less sensitive to the brightness of LEDs by utilizing a high-performance object detection model such as YOLOv8 without relying on existing algorithms. Through this, we aim to enable precise wafer focus detection using artificial intelligence.

• Smart Structures and Systems
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• v.1 no.2
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• pp.185-215
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• 2005

Advanced signal processing techniques have been long introduced and widely used in structural health monitoring (SHM) and nondestructive evaluation (NDE). In our research, we applied several signal processing approaches for our embedded ultrasonic structural radar (EUSR) system to obtain improved damage detection results. The EUSR algorithm was developed to detect defects within a large area of a thin-plate specimen using a piezoelectric wafer active sensor (PWAS) array. In the EUSR, the discrete wavelet transform (DWT) was first applied for signal de-noising. Secondly, after constructing the EUSR data, the short-time Fourier transform (STFT) and continuous wavelet transform (CWT) were used for the time-frequency analysis. Then the results were compared thereafter. We eventually chose continuous wavelet transform to filter out from the original signal the component with the excitation signal's frequency. Third, cross correlation method and Hilbert transform were applied to A-scan signals to extract the time of flight (TOF) of the wave packets from the crack. Finally, the Hilbert transform was again applied to the EUSR data to extract the envelopes for final inspection result visualization. The EUSR system was implemented in LabVIEW. Several laboratory experiments have been conducted and have verified that, with the advanced signal processing approaches, the EUSR has enhanced damage detection ability.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.27 no.11
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• pp.1525-1533
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• 2003

In the precision hot plate for wafer processing, uniform temperature of the upper plate is one of key factors affecting the quality of wafers. The state-of-the-art precision hot plates require temperature Variations less than $\pm$0.4$^{\circ}C$ during heating to 15$0^{\circ}C$, Which is difficult to be obtained only by the improvement of manufacturing techniques alone. In this study, computer aided heat transfer analysis was carried out to obtain the temperature distribution of the currently used reference hot plate for 200mm wafer. The analysis on the reference model assuming constant heat generation rate and uniform heating area showed total variation of 0.926$^{\circ}C$ at 15$0^{\circ}C$. One of the new design approaches based on the change of heating location together with different heat generation rate resulted in total variation of 0.297$^{\circ}C$ which is a 68% improvement compared to that of the reference model.