• 반도체디스플레이기술학회지
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• 제19권3호
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• pp.55-60
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• 2020

The hard mask photo-resist strip inspection system for the semiconductor wafer manufacturing process inspects the position of the circuit pattern formed on the wafer by measuring the distance from the edge of the wafer to the strip processing area. After that, it is an inspection system that enables you to check the process status in real time. Process defects can be significantly reduced by applying a tester that has not been applied to the existing wafer strip process, edge etching process, and wafer ashing process. In addition, it is a technology for localizing semiconductor process inspection equipment that can analyze the outer diameter of the wafer and the state of pattern formation, which can secure process stability and improve wafer edge yield.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2002년도 ICCAS
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• pp.55.4-55
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• 2002

In the semiconductor fabrication, particle contamination is wide-spread and one of major causes to yield loss. Extensive testing has revealed that even careful handling of wafers during processing may cause photo-resist materials to flake off wafer edges. So, to remove the photo-resist at the outer 5mm of wafers, UV(Ultraviolet) rays are exposed. WEE (Wafer Edge Exposure) process station is the system that exposes the wafer edge as prespecified by controlling the positioning mechanism and maintaining the light intensity level In this work, WEE process station has been designed so as to significantly lower the amount of particle contamination which occurs even during the most r...

• 한국결정성장학회:학술대회논문집
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• 한국결정성장학회 1996년도 The 9th KACG Technical Annual Meeting and the 3rd Korea-Japan EMGS (Electronic Materials Growth Symposium)
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• pp.88-138
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• 1996

Electronics grew up to the largest industry in the world supported by Si wafer. In near future, the Si wafer may use 300mm in diameter for economic requirement. This size wafer may use to produce large logic chip, 256Mbit DRAM, and other large complex and high density chip. Then, the quality including flatness and crustal characters may be required very high performance. And, their price should be reasonable and high quantity may be required. These requirements should be solve lot of hard problems of crystal growth, wafering mechanical processing and their cost problems. In this presentation, I may discuss following items.

• 반도체디스플레이기술학회지
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• 제19권2호
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• pp.77-81
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• 2020

Silicon wafer etching in micro electro mechanical systems (MEMS) fabrication is challenging to form 3-D structures. Well known Si-wet etch of silicon employs potassium hydroxide (KOH), tetramethylammonium hydroxide (TMAH) and sodium hydroxide (NaOH). However, the existing silicon wet etching process has a fatal disadvantage that etching of the back side of the wafer is hard to avoid. In this study, a wet etching bath for 150 mm wafers was designed to prevent back-side etching of silicon wafer, and we demonstrated the optimized process recipe to have anisotropic wet etching of silicon wafer without any damage on the backside. We also presented the design of wet bath for 300 mm wafer processing as a promising process development.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2002년도 추계학술발표강연 및 논문개요집
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• pp.48-48
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• 2002

• 대한기계학회논문집
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• 제16권4호
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• pp.609-620
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• 1992

본 연구에서는 텅스텐 할로겐 램프를 이용한 급속 열처리 장치로 웨이퍼를 가 열할 때 시간에 따라 변하는 웨이퍼의 2차원 온도 분포와 온도 구배에 의해 발생하는 열응력을 실리콘 웨이퍼의 결정방향에 따라 다른 값을 갖는 탄성계수를 고려하여 계산 하고, 슬립의 발생 시기, 웨이퍼의 가열속도와 슬립량의 관계, 그리고 웨이퍼에 발생 한 슬립의 진전 특성에 대하여 살펴보고 실험결과와 비교하였다.

• 한국항행학회논문지
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• 제13권3호
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• pp.412-418
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• 2009

본 논문에서는 노치형 웨이퍼 20~25개를 일련번호가 같은 위치에 자동으로 정렬이 되도록 하여 반도체 공정 전, 후 감지기에 의해 웨이퍼의 공정상태 파악을 용이하게 하는 시스템 개발 및 정확하게 노치를 정렬하는 보정 알고리즘, 스테핑 모터 제어 알고리즘을 제안하였다. 웨이퍼 회전 시 표면 재질이 적당한 마찰 계수를 가지며 웨이퍼의 회전으로 파티클(Particle)이 발생하지 않는 소재를 사용하여 발생을 최소화 시킬 수 있었다. 또한 미끄럼 방지를 위한 기구설계 기술을 개발하였고, 수학적 검증을 통한 성능평가를 실시하였다. 본 연구 개발 시스템은 반도체 공정 진행 중 웨이퍼의 오염 방지로 반도체 수율을 향상 시킬 수 있으며, 향후 450mm 이상의 대형 웨이퍼 생성 시에도 탄력적으로 적용 할 수 있다.

• 한국레이저가공학회:학술대회논문집
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• 한국레이저가공학회 2006년도 추계학술발표대회 논문집
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• pp.128-132
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• 2006

Low-k wafer engraving process has been investigated by using UV pico-second laser with high repetition rate. Wavelength and repetition rate of laser used in this study are 355nm and 80MHz, respectively. Main parameters of low-k wafer engraving processes are laser power, work speed, assist gas flow rate, and protective coating to eliminate debris. Results show that engraving qualities of low-k layer by using UV pico-second pulse width and high repetition rate had better kerf edge and higher work speed, compared to one by conventional laser with nano-second pulse width and low repetition rate in the range of kHz. Assist gas and protective coating to eliminate debris gave effects on the quality of engraving edge. Total engraving width and depth are obtained less than $20{\mu}m$ and $10{\mu}m$ at more than 500mm/sec work speed, respectively. We believe that engraving method by using UV pico-second laser with high repetition rate is useful one to give high work speed of laser material process.

• 한국재료학회지
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• 제15권9호
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• pp.613-619
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• 2005

The ever increasing popularity and acceptance in the market place of portable systems, such as cell phones, PDA, notebook PC, etc., are fueling effects in further miniaturizing and lowering power consumption in these systems. The dynamic power consumption due to the CPU activities and the static power consumption due to leakage currents are two major sources of power consumption. Smaller devices and a lower de voltage lead to reducing the power requirement, while better insulation and isolation of devices lead to reducing leakage currents. All these can be harnessed in the SOI (silicon-on-insulator) technology. In this study, the key aspects of the SOI technology, mainly device electrical properties and device processing steps, are briefly reviewed. The interesting materials issues, such as SOI structure formation and SOI wafer fabrication methods, are then surveyed. In particular, the recent technological innovations in two major SOI wafer fabrication methods, namely wafer bonding and SIMOX, are explored and compared in depth. The results of the study are nixed in that, although the quality of the SOI structures has shown great improvements, the processing steps are still found to be too complex. Between the two methods, no clear winner has yet emerged in terms of the product quality and cost considerations.

• 한국레이저가공학회지
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• 제6권3호
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• pp.29-35
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• 2003

In semiconductor processing, there are two types of particle contaminated onto the wafer, i.e. dry and wet state particles. In order to evaluate the cleaning performance of laser shock wave cleaning method, the removal of 1 m sized alumina particle at different particle conditions from silicon wafer has been carried out by laser-induced shock waves. It was found that the removal efficiency by laser shock cleaning was strongly dependent on the particle condition, i.e. the removal efficiency of dry alumina particle from silicon wafer was around 97％ while the efficiencies of wet alumina particle in DI water and IPA are 35％ and 55％ respectively. From the analysis of adhesion forces between the particle and the silicon substrate, the adhesion force of the wet particle where capillary force is dominant is much larger than that of the dry particle where Van der Waals force is dominant. As a result, it is seen that the particle in wet condition is much more difficult to remove from silicon wafer than the particle in dry condition by using physical cleaning method such as laser shock cleaning.