• Title/Summary/Keyword: Wafer processing

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Virtual Metrology for predicting $SiO_2$ Etch Rate Using Optical Emission Spectroscopy Data

  • Kim, Boom-Soo;Kang, Tae-Yoon;Chun, Sang-Hyun;Son, Seung-Nam;Hong, Sang-Jeen
    • Proceedings of the Korean Vacuum Society Conference
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    • 2010.02a
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    • pp.464-464
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    • 2010
  • A few years ago, for maintaining high stability and production yield of production equipment in a semiconductor fab, on-line monitoring of wafers is required, so that semiconductor manufacturers are investigating a software based process controlling scheme known as virtual metrology (VM). As semiconductor technology develops, the cost of fabrication tool/facility has reached its budget limit, and reducing metrology cost can obviously help to keep semiconductor manufacturing cost. By virtue of prediction, VM enables wafer-level control (or even down to site level), reduces within-lot variability, and increases process capability, $C_{pk}$. In this research, we have practiced VM on $SiO_2$ etch rate with optical emission spectroscopy(OES) data acquired in-situ while the process parameters are simultaneously correlated. To build process model of $SiO_2$ via, we first performed a series of etch runs according to the statistically designed experiment, called design of experiments (DOE). OES data are automatically logged with etch rate, and some OES spectra that correlated with $SiO_2$ etch rate is selected. Once the feature of OES data is selected, the preprocessed OES spectra is then used for in-situ sensor based VM modeling. ICP-RIE using 葰.56MHz, manufactured by Plasmart, Ltd. is employed in this experiment, and single fiber-optic attached for in-situ OES data acquisition. Before applying statistical feature selection, empirical feature selection of OES data is initially performed in order not to fall in a statistical misleading, which causes from random noise or large variation of insignificantly correlated responses with process itself. The accuracy of the proposed VM is still need to be developed in order to successfully replace the existing metrology, but it is no doubt that VM can support engineering decision of "go or not go" in the consecutive processing step.

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Silicon Nitride Layer Deposited at Low Temperature for Multicrystalline Solar Cell Application

  • Karunagaran, B.;Yoo, J.S.;Kim, D.Y.;Kim, Kyung-Hae;Dhungel, S.K.;Mangalaraj, D.;Yi, Jun-Sin
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2004.11a
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    • pp.276-279
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    • 2004
  • Plasma enhanced chemical vapor deposition (PECVD) of silicon nitride (SiN) is a proven technique for obtaining layers that meet the needs of surface passivation and anti-reflection coating. In addition, the deposition process appears to provoke bulk passivation as well due to diffusion of atomic hydrogen. This bulk passivation is an important advantage of PECVD deposition when compared to the conventional CVD techniques. A further advantage of PECVD is that the process takes place at a relatively low temperature of 300t, keeping the total thermal budget of the cell processing to a minimum. In this work SiN deposition was performed using a horizontal PECVD reactor system consisting of a long horizontal quartz tube that was radiantly heated. Special and long rectangular graphite plates served as both the electrodes to establish the plasma and holders of the wafers. The electrode configuration was designed to provide a uniform plasma environment for each wafer and to ensure the film uniformity. These horizontally oriented graphite electrodes were stacked parallel to one another, side by side, with alternating plates serving as power and ground electrodes for the RF power supply. The plasma was formed in the space between each pair of plates. Also this paper deals with the fabrication of multicrystalline silicon solar cells with PECVD SiN layers combined with high-throughput screen printing and RTP firing. Using this sequence we were able to obtain solar cells with an efficiency of 14% for polished multi crystalline Si wafers of size 125 m square.

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Study on Distortion Compensation of Underwater Archaeological Images Acquired through a Fisheye Lens and Practical Suggestions for Underwater Photography - A Case of Taean Mado Shipwreck No. 1 and No. 2 -

  • Jung, Young-Hwa;Kim, Gyuho;Yoo, Woo Sik
    • Journal of Conservation Science
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    • v.37 no.4
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    • pp.312-321
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    • 2021
  • Underwater archaeology relies heavily on photography and video image recording during surveillances and excavations like ordinary archaeological studies on land. All underwater images suffer poor image quality and distortions due to poor visibility, low contrast and blur, caused by differences in refractive indices of water and air, properties of selected lenses and shapes of viewports. In the Yellow Sea (between mainland China and the Korean peninsula), the visibility underwater is far less than 1 m, typically in the range of 30 cm to 50 cm, on even a clear day, due to very high turbidity. For photographing 1 m x 1 m grids underwater, a very wide view angle (180°) fisheye lens with an 8 mm focal length is intentionally used despite unwanted severe barrel-shaped image distortion, even with a dome port camera housing. It is very difficult to map wide underwater archaeological excavation sites by combining severely distorted images. Development of practical compensation methods for distorted underwater images acquired through the fisheye lens is strongly desired. In this study, the source of image distortion in underwater photography is investigated. We have identified the source of image distortion as the mismatching, in optical axis and focal points, between dome port housing and fisheye lens. A practical image distortion compensation method, using customized image processing software, was explored and verified using archived underwater excavation images for effectiveness in underwater archaeological applications. To minimize unusable area due to severe distortion after distortion compensation, practical underwater photography guidelines are suggested.

Growth of Aluminum Nitride Thin Films by Atomic Layer Deposition and Their Applications: A Review (원자층 증착법을 이용한 AlN 박막의 성장 및 응용 동향)

  • Yun, Hee Ju;Kim, Hogyoung;Choi, Byung Joon
    • Korean Journal of Materials Research
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    • v.29 no.9
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    • pp.567-577
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    • 2019
  • Aluminum nitride (AlN) has versatile and intriguing properties, such as wide direct bandgap, high thermal conductivity, good thermal and chemical stability, and various functionalities. Due to these properties, AlN thin films have been applied in various fields. However, AlN thin films are usually deposited by high temperature processes like chemical vapor deposition. To further enlarge the application of AlN films, atomic layer deposition (ALD) has been studied as a method of AlN thin film deposition at low temperature. In this mini review paper, we summarize the results of recent studies on AlN film grown by thermal and plasma enhanced ALD in terms of processing temperature, precursor type, reactant gas, and plasma source. Thermal ALD can grow AlN thin films at a wafer temperature of $150{\sim}550^{\circ}C$ with alkyl/amine or chloride precursors. Due to the low reactivity with $NH_3$ reactant gas, relatively high growth temperature and narrow window are reported. On the other hand, PEALD has an advantage of low temperature process, while crystallinity and defect level in the film are dependent on the plasma source. Lastly, we also introduce examples of application of ALD-grown AlN films in electronics.

Permeability of the Lateral Air Flow through Unstructured Pillar-like Nanostructures (비정형 기둥 형상을 가진 나노구조에서의 가스 투과성 실험 연구)

  • Hyewon Kim;Hyewon Lim;Jeong Woo Park;Sangmin Lee;Hyungmo Kim
    • Tribology and Lubricants
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    • v.39 no.5
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    • pp.197-202
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    • 2023
  • Recently, research on experimental and analytical techniques utilizing microfluidic devices has been pursued. For example, lab-on-a-chip devices that integrate micro-devices onto a single chip for processing small sample quantities have gained significant attention. However, during sample preparation, unnecessary gases can be introduced into the internal channels, thus, impeding device flow and compromising specific function efficiency, including that of analysis and separation. Several methods have been proposed to mitigate this issue, however, many involve cumbersome procedures or suffer from complexities owing to intricate structures. Recently, some approaches have been introduced that utilize hydrophobic device structures to remove gases within channels. In such cases, the permeability of gases passing through the structure becomes a crucial performance factor. In this study, a method involving the deposition and sintering of diluted Ag-ink onto a silicon wafer surface is presented. This is followed by unstructured nano-pattern creation using a Metal Assisted Chemical Etching (MACE) process, which yields a nanostructured surface with unstructured pillar shapes. Subsequently, gas permeability in the spaces formed by these surface structures is investigated. This is achieved by experiments conducted to incorporate a pressure chamber and measure gas permeability. Trends are subsequently analyzed by comparing the results with existing theories. Finally, it can be confirmed that the significance of this study primarily lies in its capability to effectively evaluate gas permeability through unstructured pillar-like nanostructures, thus, providing quantitative values for the appropriate driving pressure and expected gas removal time in practical device operation.

The Effect of Mask Patterns on Microwire Formation in p-type Silicon (P-형 실리콘에서 마이크로 와이어 형성에 미치는 마스크 패턴의 영향)

  • Kim, Jae-Hyun;Kim, Kang-Pil;Lyu, Hong-Kun;Woo, Sung-Ho;Seo, Hong-Seok;Lee, Jung-Ho
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.11a
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    • pp.418-418
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    • 2008
  • The electrochemical etching of silicon in HF-based solutions is known to form various types of porous structures. Porous structures are generally classified into three categories according to pore sizes: micropore (below 2 nm in size), mesopore (2 ~ 50 nm), and macropore (above 50 nm). Recently, the formation of macropores has attracted increasing interest because of their promising characteristics for an wide scope of applications such as microelectromechanical systems (MEMS), chemical sensors, biotechnology, photonic crystals, and photovoltaic application. One of the promising applications of macropores is in the field of MEMS. Anisotropic etching is essential step for fabrication of MEMS. Conventional wet etching has advantages such as low processing cost and high throughput, but it is unsuitable to fabricate high-aspect-ratio structures with vertical sidewalls due to its inherent etching characteristics along certain crystal orientations. Reactive ion dry etching is another technique of anisotropic etching. This has excellent ability to fabricate high-aspect-ratio structures with vertical sidewalls and high accuracy. However, its high processing cost is one of the bottlenecks for widely successful commercialization of MEMS. In contrast, by using electrochemical etching method together with pre-patterning by lithographic step, regular macropore arrays with very high-aspect-ratio up to 250 can be obtained. The formed macropores have very smooth surface and side, unlike deep reactive ion etching where surfaces are damaged and wavy. Especially, to make vertical microwire or nanowire arrays (aspect ratio = over 1:100) on silicon wafer with top-down photolithography, it is very difficult to fabricate them with conventional dry etching. The electrochemical etching is the most proper candidate to do it. The pillar structures are demonstrated for n-type silicon and the formation mechanism is well explained, while such a experimental results are few for p-type silicon. In this report, In order to understand the roles played by the kinds of etching solution and mask patterns in the formation of microwire arrays, we have undertaken a systematic study of the solvent effects in mixtures of HF, dimethyl sulfoxide (DMSO), iso-propanol, and mixtures of HF with water on the structure formation on monocrystalline p-type silicon with a resistivity with 10 ~ 20 $\Omega{\cdot}cm$. The different morphological results are presented according to mask patterns and etching solutions.

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Temperature Dependence on Dry Etching of $ZrO_2$ Thin Films in $Cl_2/BCl_3$/Ar Inductively Coupled Plasma ($Cl_2/BCl_3$/Ar 유도 결합 플라즈마에서 온도에 따른 $ZrO_2$ 박막의 식각)

  • Yang, Xue;Kim, Dong-Pyo;Lee, Cheol-In;Um, Doo-Seung;Kim, Chang-Il
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.11a
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    • pp.145-145
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    • 2008
  • High-k materials have been paid much more attention for their characteristics with high permittivity to reduce the leakage current through the scaled gate oxide. Among the high-k materials, $ZrO_2$ is one of the most attractive ones combing such favorable properties as a high dielectric constant (k= 20 ~ 25), wide band gap (5 ~ 7 eV) as well as a close thermal expansion coefficient with Si that results in good thermal stability of the $ZrO_2$/Si structure. During the etching process, plasma etching has been widely used to define fine-line patterns, selectively remove materials over topography, planarize surfaces, and trip photoresist. About the high-k materials etching, the relation between the etch characteristics of high-k dielectric materials and plasma properties is required to be studied more to match standard processing procedure with low damaged removal process. Among several etching techniques, we chose the inductively coupled plasma (ICP) for high-density plasma, easy control of ion energy and flux, low ownership and simple structure. And the $BCl_3$ was included in the gas due to the effective extraction of oxygen in the form of $BCl_xO_y$ compounds. During the etching process, the wafer surface temperature is an important parameter, until now, there is less study on temperature parameter. In this study, the etch mechanism of $ZrO_2$ thin film was investigated in function of $Cl_2$ addition to $BCl_3$/Ar gas mixture ratio, RF power and DC-bias power based on substrate temperature increased from $10^{\circ}C$ to $80^{\circ}C$. The variations of relative volume densities for the particles were measured with optical emission spectroscopy (OES). The surface imagination was measured by scanning emission spectroscope (SEM). The chemical state of film was investigated using energy dispersive X-ray (EDX).

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The Pad Recovery as a function of Diamond Shape on Diamond Disk for Metal CMP (Metal CMP 용 컨디셔너 디스크 표면에 존재하는 다이아몬드의 형상이 미치는 패드 회복력 변화)

  • Kim, Kyu-Chae;Kang, Young-Jae;Yu, Young-Sam;Park, Jin-Goo;Won, Young-Man;Oh, Kwang-Ho
    • Journal of the Microelectronics and Packaging Society
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    • v.13 no.3 s.40
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    • pp.47-51
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    • 2006
  • Recently, CMP (Chemical Mechanical Polishing) is one of very important processing in semiconductor technology because of large integration and application of design role. CMP is a planarization process of wafer surface using the chemical and mechanical reactions. One of the most important components of the CMP system is the polishing pad. During the CMP process, the pad itself becomes smoother and glazing. Therefore it is necessary to have a pad conditioning process to refresh the pad surface, to remove slurry debris and to supply the fresh slurry on the surface. A conditioning disk is used during the pad conditioning. There are diamonds on the surface of diamond disk to remove slurry debris and to polish pad surface slightly, so density, shape and size of diamond are very important factors. In this study, we characterized diamond disk with 9 kinds of sample.

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The Measurement of Folacin Content in Korean Foods -Part 3. Folate Distribution in Various Foods- (한국 상용 식품의 엽산 분석에 관한 연구 -제 3 보-)

  • Kim, Young-Min
    • Journal of Nutrition and Health
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    • v.12 no.2
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    • pp.53-63
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    • 1979
  • In continuation of the previous $studies^{2{\sim}3)}$, the folate activity levels in 226 Korean food items were determined by a modified microbiological assay with Lactobacillus casei. There was a large variation in folate activity between the different food groups as well as between each individual food. There was also a wide variation in the biologic availability of folate in foods and the different forms of the folate with different foods in varying amounts. Data showed that almost always, foods cooked and/or processed were lower in folate activity than fresh or raw food and the amount of the loss varied greatly in each food. In calculating dietary intake, total rather than free folate activity levels should he used. In addition, loss of folate activity during cooking and processing of foods should be considered as a major concern for appraising diets and food supplies. Among all assayed food items, including Part $I^{2)}}$ and $I^{3)}$, yeast 2800. ug total per 100g the highest folate level. Soybean, spinach, Shepherd's purse and liter of beef and pork had over 100 ug total per 100 g folate activity. Folate ranging over 50 ug total per 100 g was found in all dried legumes, nuts and seeds assayed, Garland Chrysanthemum, leek, mugwort, wafer cress, asparagus, e99 folk and beef kidney. Wheat, sweet Potatoes,dried fungus, green onion, hotrod pepper, lettuce, radish and some fermented soybeen products had considerably higher folate content ranging around 40 ug total per 100 g. Substantial amounts of folate were not found in many food groups, and among specific groups, in part in starch, sweets, fruits, meat, fish, milk, and cooked and processed foods. Soused fish, oils and fats, beverages, liquor and seasonings, other than fermented soybean products, had almost no folate.

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Design of PMOS-Diode Type eFuse OTP Memory IP (PMOS-다이오드 형태의 eFuse OTP IP 설계)

  • Kim, Young-Hee;Jin, Hongzhou;Ha, Yoon-Gyu;Ha, Pan-Bong
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.13 no.1
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    • pp.64-71
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    • 2020
  • eFuse OTP memory IP is required to trim the analog circuit of the gate driving chip of the power semiconductor device. Conventional NMOS diode-type eFuse OTP memory cells have a small cell size, but require one more deep N-well (DNW) mask. In this paper, we propose a small PMOS-diode type eFuse OTP memory cell without the need for additional processing in the CMOS process. The proposed PMOS-diode type eFuse OTP memory cell is composed of a PMOS transistor formed in the N-WELL and an eFuse link, which is a memory element and uses a pn junction diode parasitic in the PMOS transistor. A core driving circuit for driving the array of PMOS diode-type eFuse memory cells is proposed, and the SPICE simulation results show that the proposed core circuit can be used to sense post-program resistance of 61㏀. The layout sizes of PMOS-diode type eFuse OTP memory cell and 512b eFuse OTP memory IP designed using 0.13㎛ BCD process are 3.475㎛ × 4.21㎛ (= 14.62975㎛2) and 119.315㎛ × 341.95㎛ (= 0.0408mm2), respectively. After testing at the wafer level, it was confirmed that it was normally programmed.