• Proceedings of the Korean Operations and Management Science Society Conference
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• 2002.05a
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• pp.285-292
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• 2002

A cluster tool for semiconductor manufacturing is an integrated device that consists of several single wafer processing modules and a wafer transport module based on a robot. The distributed module controllers are integrated by an inter-module communication network and coordinated by a centralized controller, called a cluster tool controller (CTC). Since the CTC monitors and coordinates the distributed complex module controllers for advanced process control, complex commuication messaging and services between the CTC and the module controllers are required. A SEMI standard, CTMC(Cluster Tool Module Communication), specifies application-level communication service requirements for inter-module communication. We propose the use of high-level fieldbuses, for instance. PROFIBUS-FMS, for implementing CTMC since the high-level fieldbuses are well suited for complex real-time distributed manufacturing control applications. We present a way of implementing CTMC using PROFIBUS-FMS as the communication enabler. We first propose improvements of a key object of CTMC for material transfer and the part transfer protocol to meet the functional requirements of modem advanced cluster tools. We also discuss mapping objects and services of CTMC to PROFIBUS-FMS communication objects and services. Finally, we explain how to implement the mappings.

• Transactions on Electrical and Electronic Materials
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• v.7 no.4
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• pp.163-166
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• 2006

The dishing and the erosion were evaluated on the tungsten CMP process with conventional and new developed slurry. The tungsten thin film was polished by orbital polishing equipment. Commercial pattern wafer was used for the evaluation. Both slurries were pre tested on the oxide region on the wafer surface and the removal rate was not different very much. At the pattern density examination, the erosion performance was increased at all processing condition due to the reduction of thickness loss in new slurry. However, the dishing thickness was not remarkably changed at high pattern density despite of the improvement at low pattern density. At the large pad area, the reduction of dishing thickness was clearly found at new tungsten slurry.

• Journal of the Korean Vacuum Society
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• v.16 no.1
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• pp.74-78
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• 2007

Much interests has been drawn for noble micro-engineering processes for the continuous size reduction on bulk materials from the field of micro-electronics with much downsized IC chips. A traditional microprocessing based on mechanical blade as well as a relatively long pulsed laser usually influence the physico-chemical properties of intact materials when the techniques are applied to process materials with a spatial resolution less than 10 microns. Meanwhile, ultrafast laser pulses are known to exhibit a very small heat-affect zone(HAE) compared to the traditional laser processing and to be applicable for the new functional materials with high performance in optical and electrical properties. In this report, we will review in brief the recent research works on the enhancement of micro-cutting speed of thin silicon wafer as well as the formation of Ge nanostructures based on ultrafast laser pulses.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.647-650
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• 2006

Low temperature polycrystalline silicon (LTPS) technology using a high power laser have been widely applied to thin film transistors (TFTs) for liquid crystal, organic light emitting diode (OLED) display, driver circuit for system on glass (SOG) and static random access memory (SRAM). Recently, the semiconductor industry is continuing its quest to create even more powerful CPU and memory chips. This requires increasing of individual device speed through the continual reduction of the minimum size of device features and increasing of device density on the chip. Moreover, the flat panel display industry also need to be brighter, with richer more vivid color, wider viewing angle, have faster video capability and be more durable at lower cost. Kornic Systems Co., Ltd. developed the $KORONA^{TM}$ LTP/GLTP series - an innovative production tool for fabricating flat panel displays and semiconductor devices - to meet these growing market demands and advance the volume production capabilities of flat panel displays and semiconductor industry. The $KORONA^{TM}\;LTP/GLTP$ series using DPSS laser and XeCl excimer laser is designed for the new generation of the wafer & FPD glass annealing processing equipment combining advanced low temperature poly-silicon (LTPS) crystallization technology and object-oriented software architecture with a semistandard graphical user interface (GUI). These leading edge systems show the superior annealing ability to the conventional other method. The $KORONA^{TM}\;LTP/GLTP$ series provides technical and economical benefits of advanced annealing solution to semiconductor and FPD production performance with an exceptional level of productivity. High throughput, low cost of ownership and optimized system efficiency brings the highest yield and lowest cost per wafer/glass on the annealing market.

• Journal of the Computational Structural Engineering Institute of Korea
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• v.17 no.3
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• pp.241-249
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• 2004

There is an over head hoist transporter(OHT) by the system for delivering the wafer in semiconductor processing. The transfer system consist of carrier, vehicle, rail and support. The Tail supporting the wafer and the transfer system should maintain enough strength and stiffness. To achieve lightness and enough strength and stiffness, optimization algorithm should be introduced in design process. In this study, two kinds of section shapes as L-type, C-type is carried out the structure analysis and optimization. Total weight of rail is to be minimized while displacement should not exceed limit. To improve the initial model, topology optimization is done by the plain problem. Size optimization is done with 3D solid element and PLBA algorithm, the RQP algorithm. The weight of optimum model as L-type, C-type is decreased by 2.3%, 10% respectively. It is improved better than the initial model in the strength and stiffness of the structure.

• Proceedings of the Korea Information Processing Society Conference
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• 2000.10a
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• pp.703-706
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• 2000

반도체 제조 공정의 효율적인 제어와 감시를 위한 모니터링 시스템을 구성하기 위해서는 장비가 가진 특성과 시스템 환경에서 요구되는 조건들과 동작 상태 둥을 사용자 인터페이스를 통하여 한 눈에 감시할 수 있는 화면 레이아웃이 요구된다. 본 논문에서는 차세대 반도체 장비인 300mm 웨이퍼 가공용 Spinner 의 MMI 개발을 목표로 하여 장비의 구성 요소들의 선택적 접속에 따라서 사용자 인터페이스용 레이아웃을 능동적으로 설계하는 방법에 대하여 기술하였다. 장비를 구성하는 기본 요소들간의 관계를 정의하고, 장비의 사양과 웨이퍼의 가공 목적에 따라 구성 요소들을 자동으로 유연성있게 배치하도록 하였다.

• Proceedings of the Korean Society of Laser Processing Conference
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• 2006.06a
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• pp.123-128
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• 2006

We constructed a micro-patterning system that build patterns on a photoresist coated wafer using laser direct writing system. Confocal microscope system was adapted for real-time auto-focusing of the laser writing lens to generate lines of uniform width.

• The Transactions of the Korea Information Processing Society
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• v.6 no.5
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• pp.1385-1392
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• 1999

This paper describes the design of the monitoring system for monitoring the current status and indirect controlling of the Wet Station Equipment which is used for cleaning the wafer. Most of the conventional monitoring system depend on the special hardware and software. Basic design goal of monitoring system is provide the convenience for the use and the portability for the system. In order for the system to fulfil its requirements, it was designed using GUI (Graphical User Interface) facility based on the windows NT environment of IBM PC compatible and EtherNet board based on the TCP/IP protocol.

• Proceedings of the Korea Information Processing Society Conference
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• 2001.04a
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• pp.345-348
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• 2001

반도체에 이용되는 실리콘웨이퍼 생산에 있어 평탄도는 가장 중요한 요소 중 하나이다. 실리콘웨이퍼의 평탄도는 POLISHING이라는 공정과정을 통하여 측정하고 제어하고 있는데 현재 측정장비에서 보여주는 웨이퍼의 모양을 사람에 의해 제어하고 있어 경험이 필요하고 일일이 사람이 체크해야하는 번거로움이 있다. 따라서 평탄도가 시스템에 의해 자동적으로 측정되고 제어할 필요가 있다. 본 연구는 웨이퍼의 3차원 형상을 측정하여 보여주는 장비에서 이미지와 함께 나타나는 몇 개의 정량적인 항목을 이용하여 웨이퍼의 단면도를 추정하는 알고리즘을 제안함으로 평탄도가 자동으로 측정될 수 있도록 하였다. 이 알고리즘은 Spline보간법을 이용하였고 웨이퍼의 특정단면 뿐만 아니라 임의의 단면도도 추정할 수 있으며 수치실험을 통해 Lagrange보간법과 비교하여 그 효율성을 입증하였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2001.04a
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• pp.255-258
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• 2001

테스트 시스템(Test System)은 반도체 제품을 웨이퍼(Wafer) 또는 완성된 제품 상태 하에서 전기적 특성과 성능을 검사하고 그 결과를 산출해내는 검사장치이다. 테스트 시스템은 크게 하드웨어와 소프트웨어로 이루어져 있으며 시스템을 제어하고 사용자 인터페이스 및 각종 자료를 처리하는 소프트웨어는 그 중요성이 한층 더 부각되고 있다. 그러나 국내 고성능의 테스트 시스템을 개발하는 기업들의 하드웨어 개발은 잘 이루어지고 있으나 소프트웨어의 개발은 어려운 실정이다. 본 논문에서는 테스트 시스템에서 사용하고 있는 테스트 프로그램의 문제점을 지적하고, 문제점을 해결할 수 있는 가상기계를 설계한다. 그리고 가상기계를 테스트 관리 프로그램 내에 내장하여 테스트관리 시스템의 소프트웨어를 향상시키고자 한다.