• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.10
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• pp.1553-1571
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• 1993

A significant amount of research has focused on the development of highly parallel architectures to obtain far more computational power than conventional computer systems. These architectures usually comprise of a large number of processors communicating through an interconnection network. The VLSI (Very Large Scale Integration) and WSI (Wafer Scale Integration) cellular arrays form one important class of those parallel architectures, and consist of a large number of simple processing cells, all on a single chip or wafer, each interconnected only to its neighbors. This paper studies three fundamental issues in these arrays : fault-tolerant reconfiguration. functional reconfiguration, and their integration. The paper examines conventional techniques, and gives an in-depth discussion about fault-tolerant reconfiguration and functional reconfiguration, presenting testing control strategy, configuration control strategy, steps required f4r each reconfiguration, and other relevant topics. The issue of integrating fault tolerant reconfiguration and functional reconfiguration has been addressed only recently. To tackle that problem, the paper identifies the relation between fault tolerant reconfiguration and functional reconfiguration, and discusses appropriate testing and configuration control strategy for integrated reconfiguration on VLSI and WSI cellular arrays.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2002.10a
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• pp.1033-1036
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• 2002

Wafer bonding methods such as fusion and anodic bonding suffer from high temperature treatment, long processing time, and possible damage to the micro-scale sensor or actuators. In the localized bonding process, beating was conducted locally while the whole wafer is maintained at a relatively low temperature. But previous research of localized heating has some problems, such as non-uniform soldering due to non-uniform heating and micro crack formation on the glass capsule by thermal stress effect. To address this non-uniformity problem, a new heater configuration is being proposed. By keeping several points on the heater strip at calculated and constant potential, more uniform heating, hence more reliable wafer bonding could be achieved. The proposed scheme has been successfully demonstrated, and the result shows that it will be very useful in hermetic packaging. Less than 0.2 ㎫ contact Pressure were used for bonding with 150 ㎃ current input for 50${\mu}{\textrm}{m}$ width, 2${\mu}{\textrm}{m}$ height and 8mm $\times$ 8mm, 5mm$\times$5mm, 3mm $\times$ 3mm sized phosphorus-doped poly-silicon micro heater. The temperature can be raised at the bonding region to 80$0^{\circ}C$, and it was enough to achieve a strong and reliable bonding in 3minutes. The IR camera test results show improved uniformity in heat distribution compared with conventional micro heaters. For gross leak check, IPA (Isopropanol Alcohol) was used. Since IPA has better wetability than water, it can easily penetrate small openings, and is more suitable for gross leak check. The pass ratio of bonded dies was 70%, for conventional localized heating, and 85% for newly developed FP scheme. The bonding strength was more than 30㎫ for FP scheme packaging, which shows that FP scheme can be a good candidate for micro scale hermetic packaging.

• The KIPS Transactions:PartD
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• v.11D no.3
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• pp.709-716
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• 2004

This paper describes an intelligent real-time monitoring system of a semiconductor processing equipment, which determines normal or not for a wafer in processing, using multiple time-series pattern recognition. The proposed system consists of three phases, initialization, learning and real-time prediction. The initialization phase sets the weights and tile effective steps for all parameters of a monitoring equipment. The learning phase clusters time series patterns, which are producted and fathered for processing wafers by the equipment, using LBG algorithm. Each pattern has an ACI which is measured by a tester at the end of a process The real-time prediction phase corresponds a time series entered by real-time with the clustered patterns using Dynamic Time Warping, and finds the best matched pattern. Then it calculates a predicted ACI from a combination of the ACI, the difference and the weights. Finally it determines Spec in or out for the wafer. The proposed system is tested on the data acquired from etching device. The results show that the error between the estimated ACI and the actual measurement ACI is remarkably reduced according to the number of learning increases.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.13 no.3
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• pp.53-60
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• 2004

We have developed and manufactured an experimental ultrasonic polishing machine with frequency of 20kHz at the power of vibration 1.7㎾ for effective ultrasonic polishing in processing of high hardness material. Design of the horn is performed by the FEM analysis. The following conclusions were empirically deduced through experimental results to clarify the major elements which affect the surface roughness during the ultrasonic process by following the experimental plans. The ultrasonic polishing machine has been developed in parts of structure part, ultrasonic generator, vibrator. We were able to process the high hardness material without difficulty as a result of ultrasonic polishing by utilizing the groove added step-type horn. Through analyzing by applying the experimental plans, the rotating speed of the horn was determined to be the major factor in influencing the surface roughness. In the case of ceramic, wafer, we were able to obtain good surface roughness when the feed rate and the ultrasonic output were higher. Because the load on slurry particle increases when the ultrasonic output is higher, the processed surface becomes worse in the case of optical glass.

• Transactions of Materials Processing
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• v.15 no.1 s.82
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• pp.9-14
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• 2006

In the present research, the simultaneous punching of ultra small size hole of $2\~10\;{\mu}m$ in diameter on flat rolled thin metal foils was conducted with elastic polymer punch. Workpiece used in the present investigation were the rolled pure copper of $3{\mu}m$ in thickness and CP titanium of 1.5fm in thickness. The metal foils were punched with the dies and arrays of circular and rectangular holes were made. The process set-up is similar to that of the flexible rubber pad farming or Guerin process. Arrays of holes were punched successfully in one step forming. The punched holes were examined in terms of their dimensions. The effects of the wafer die hole dimension and heat treatment of the workpiece on ultra small size hole formation of the thin foil were discussed. The process condition such as proper die shape, pressure, pressure rate and diameter-thickness ratio (d/t) were also discussed. The results in this paper show that the present method can be successfully applied to the fabrication of ultra small size hole away in a one step operation.

• International Journal of Internet, Broadcasting and Communication
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• v.12 no.2
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• pp.30-36
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• 2020

We demonstrated a successful fabrication of 4" Gallium Nitride (GaN)/Diamond High Electron Mobility Transistors (HEMTs) incorporated with Inner Slot Via Hole process. We made in manufacturing technology of 4" GaN/Diamond HEMT wafers in a compound semiconductor foundry since reported [1]. Wafer thickness uniformity and wafer flatness of starting GaN/Diamond wafers have improved greatly, which contributed to improved processing yield. By optimizing Laser drilling techniques, we successfully demonstrated a through-substrate-via process, which is last hurdle in GaN/Diamond manufacturing technology. To fully exploit Diamond's superior thermal property for GaN HEMT devices, we include Aluminum Nitride (AlN) barrier in epitaxial layer structure, in addition to conventional Aluminum Gallium Nitride (AlGaN) barrier layer. The current collapse revealed very stable up to Vds = 90 V. The trapping behaviors were measured Emission Microscope (EMMI). The traps are located in interface between Silicon Nitride (SiN) passivation layer and GaN cap layer.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1108-1109
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• 2008

To survive in outdoor environments, photovoltaic modules rely on packaging materials to provide requisite durability. We analyzed the properties of encapsulant materials that are important for photovoltaic module packaging. Recently, the thickness of solar cell gets thinner to reduce the quantity of silicon. And the reduced thickness make it easy to be broken while PV module fabrication process. Solar cell's micro cracks are increasing the breakage risk over the whole value chain from the wafer to the finished module, because the wafer or cell is exposed to tensile stress during handling and processing. This phenomenon might make PV module's maximum power and durability down. So, when using thin solar cell for PV module fabrication, it is needed to optimize the material and fabrication condition which is quite different from normal thick solar cell process. Normally, gel-content of EVA sheet should be higher than 80% so PV module has long term durability. But high gel-content characteristic might cause micro-crack on solar cell. In this experiment, we fabricated several specimen by varying curing temperature and time condition. And from the gel-content measurement, we figure the best fabrication condition. Also we examine the crack generation phenomenon during experiment.

• Journal of the Korean Society for Precision Engineering
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• v.22 no.7 s.172
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• pp.27-37
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• 2005

Direct writing technology on the silicon wafer surface is used to reduce the size of the chip as the miniature trend in electronic circuit. In order to improve the productivity and efficiency, the real time quality estimation is very important in each semiconductor process. In laser marking, marking quality is determined by readability which is dependant on the contrast of surface, the line width, and the melting depth. Many researchers have tried to find theoretical and numerical estimation models fur groove geometry. However, these models are limited to be applied to the real system. In this study, the estimation system for the line width during the laser marking was proposed by process monitoring method. The light intensity emitted by plasma which is produced when irradiating the laser to the silicon wafer was measured using the optical sensor. Because the laser marking is too fast to measure with external sensor, we build up the coaxial monitoring system. Analysis for the correlation between the acquired signals and the line width according to the change of laser power was carried out. Also, we developed the models enabling the estimation of line width of the laser marking through the statistical regression models and may see that their estimating performances were excellent.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.182-182
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• 2012

Plasma etching is used in various semiconductor processing steps. In plasma etcher, optical- emission spectroscopy (OES) is widely used for in-situ endpoint detection. However, the sensitivity of OES is decreased if polymer is deposited on viewport or the proportion of exposed area on the wafer is too small. Because of these problems, the object is to investigate the suitability of using plasma impedance monitoring (PIM) and self plasma optical emission spectrocopy (SPOES) with statistical approach for in-situ endpoint detection. The endpoint was determined by impedance signal variation from I-V monitor (VI probe) and optical emission signal from SPOES. However, the signal variation at the endpoint is too weak to determine endpoint when $SiO_2$ and SiNx layers are etched by fluorocarbon on inductive coupled plasma (ICP) etcher, if the proportion of $SiO_2$ and SiNx area on Si wafer are small. Therefore, modified principal component analysis (mPCA) is applied to them for increasing sensitivity. For verifying this method, detected endpoint from impedance monitoring is compared with optical emission spectroscopy.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.32-32
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• 2011

Plasma etching is used in microelectronic processing for patterning of micro- and nano-scale devices. Commonly, optical emission spectroscopy (OES) is widely used for real-time endpoint detection for plasma etching. However, if the viewport for optical-emission monitoring becomes blurred by polymer film due to prolonged use of the etching system, optical-emission monitoring becomes impossible. In addition, when the exposed area ratio on the wafer is small, changes in the optical emission are so slight that it is almost impossible to detect the endpoint of etching. For this reason, as a simple method of detecting variations in plasma without contamination of the reaction chamber at low cost, a method of measuring plasma impedance is being examined. The object in this research is to investigate the suitability of using plasma impedance monitoring (PIM) with statistical approach for real-time endpoint detection of $SiO_2$ etching. The endpoint was determined by impedance signal variation from I-V monitor (VI probe). However, the signal variation at the endpoint is too weak to determine endpoint when $SiO_2$ film on Si wafer is etched by fluorocarbon plasma on inductive coupled plasma (ICP) etcher. Therefore, modified principal component analysis (mPCA) is applied to them for increasing sensitivity. For verifying this method, detected endpoint from impedance analysis is compared with optical emission spectroscopy (OES). From impedance data, we tried to analyze physical properties of plasma, and real-time endpoint detection can be achieved.