• Title/Summary/Keyword: Wafer processing

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Study on auto focusing system of laser beam by using fiber confocal method (파이버 공초점법을 이용한 레이저 빔 자동 초점 제어 장치에 관한 연구)

  • Moon, Seong-Wook;King, Sun-Hum;Kim, Jong-Bae;Bae, Han-Seong;Nam, Gi-Jung
    • Proceedings of the Korean Society of Laser Processing Conference
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    • 2006.11a
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    • pp.41-45
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    • 2006
  • Auto focusing system to find optimized focal position of laser beam used for material process has been investigated by using fiber confocal method. Wavelength of laser diode (LD) and diameter of single-mode fiber we 780nm and $5.3{\mu}m$, respectively. Intensity distributions of beam reflected from the surface of mirror and silicon bare wafer have been observed in a gaussian form. Experimental results show that focal position obtained by LD is shifted from one observed from surface scribed by laser about $80{\mu}m$. It is due to the difference of wavelength and each divergence of between LD and laser used for material process. It is confirmed that auto focusing control system through position calibration has operated steadily.

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Development of Confocal Imaging System for Wafer Inspection (개발 웨이퍼 검사위한 Confocal 이미징 시스템의 개발)

  • Ko, Kuk-Won;Nguyen, Cong Dai;Koh, Kyung-Cheol
    • Proceedings of the KAIS Fall Conference
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    • 2010.05a
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    • pp.108-112
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    • 2010
  • Confocal Imaging System is an essential machine for a wide range of inspection wafer. For concurrent and fast acquiring the image data of four channels, the new image acquisition system used the protocol of camera-link standard with the full mode of configuration in interconnection with a frame grabber integrated in a computer, which is popularly used for many cameras, so the programming environment of image processing is optional such as Visual C++, Matlab. In addition, many conventional methods were coordinately used for contribution to build the high quality of images for precise processing analog signals of PhotoMutiplier Tubes(PMTs), accurate control of scanning device, sensitivity of PMTs, and laser source. The prototype of new image acquisition system, could meet the goal of development, it is used in LSCM for high content screening to investigation the processes of elements of living specimens at the same time by simultaneous grab image data on 4 PMTs channels.

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Optimization of Etching Profile in Deep-Reactive-Ion Etching for MEMS Processes of Sensors

  • Yang, Chung Mo;Kim, Hee Yeoun;Park, Jae Hong
    • Journal of Sensor Science and Technology
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    • v.24 no.1
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    • pp.10-14
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    • 2015
  • This paper reports the results of a study on the optimization of the etching profile, which is an important factor in deep-reactive-ion etching (DRIE), i.e., dry etching. Dry etching is the key processing step necessary for the development of the Internet of Things (IoT) and various microelectromechanical sensors (MEMS). Large-area etching (open area > 20%) under a high-frequency (HF) condition with nonoptimized processing parameters results in damage to the etched sidewall. Therefore, in this study, optimization was performed under a low-frequency (LF) condition. The HF method, which is typically used for through-silicon via (TSV) technology, applies a high etch rate and cannot be easily adapted to processes sensitive to sidewall damage. The optimal etching profile was determined by controlling various parameters for the DRIE of a large Si wafer area (open area > 20%). The optimal processing condition was derived after establishing the correlations of etch rate, uniformity, and sidewall damage on a 6-in Si wafer to the parameters of coil power, run pressure, platen power for passivation etching, and $SF_6$ gas flow rate. The processing-parameter-dependent results of the experiments performed for optimization of the etching profile in terms of etch rate, uniformity, and sidewall damage in the case of large Si area etching can be summarized as follows. When LF is applied, the platen power, coil power, and $SF_6$ should be low, whereas the run pressure has little effect on the etching performance. Under the optimal LF condition of 380 Hz, the platen power, coil power, and $SF_6$ were set at 115W, 3500W, and 700 sccm, respectively. In addition, the aforementioned standard recipe was applied as follows: run pressure of 4 Pa, $C_4F_8$ content of 400 sccm, and a gas exchange interval of $SF_6/C_4F_8=2s/3s$.

A Case Study for Estimating the Defect Rate of PLC Using Sampling Inspection and Improving the Cause of Defects (샘플링검사를 이용한 PLC의 불량률 추정 및 불량원인 개선 사례연구)

  • Moon, In-Sun;Lee, Dong-Hyung
    • Journal of Korean Society of Industrial and Systems Engineering
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    • v.44 no.4
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    • pp.128-135
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    • 2021
  • WDM(Wavelength Division Multiplexing) is called a wavelength division multiplexing optical transmission method and is a next-generation optical transmission technology. Case company F has recently developed and sold PLC(Planar Lightwave Circuit), a key element necessary for WDM system production. Although Chinese processing companies are being used as a global outsourcing strategy to increase price competitiveness by lowering manufacturing unit prices, the average defect rate of products manufactured by Chinese processing companies is more than 50%, causing many problems. However, Chinese processing companies are trying to avoid responsibility, saying that the cause of the defect is the defective PLC Wafer provided by Company F. Therefore, in this study, the responsibility of the PLC defect is clearly identified through estimating the defect rate of PLC using the sampling inspection method, and the improvement plan for each cause of the PLC defect for PLC yeild improvement is proposed. The result of this research will greatly contribute to eliminating the controversy over providing the cause of defects between global outsourcing companies and the head office. In addition, it is expected to form a partnership with Company F and a Chinese processing company, which will serve as a cornerstone for successful global outsourcing. In the future, it is necessary to increase the reliability of the PLC yield calculation by extracting more precisely the number of defects.

3D Packaging Technology Using Femto Laser (팸토초 레이저를 이용한 3차원 패키징 기술)

  • Kim, Ju-Seok;Sin, Yeong-Ui;Kim, Jong-Min;Han, Seong-Won
    • Proceedings of the KWS Conference
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    • 2006.10a
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    • pp.190-192
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    • 2006
  • The 3-dimensional(3D) chip stacking technology is one of the leading technologies to realize a high density and high performance system in package(SIP). It could be found that it is the advanced process of through-hole via formation with the minimum damaged on the Si-wafer. Laser ablation is very effective method to penetrate through hole on the Si-wafer because it has the advantage that formed under $100{\mu}m$ diameter through-hole via without using a mask. In this paper, we studied the optimum method for a formation of through-hole via using femto-second laser heat sources. Furthermore, the processing parameters of the specimens were several conditions such as power of output, pulse repetition rate as well as irradiation method and time. And also the through-hole via form could be investigated and analyzed by microscope and analyzer.

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A study on wet etching for silicon membrane construction formation (실리콘 Membrane 구조 형성을 위한 Wet Etching에 관한 연구)

  • 김동수;정원채
    • Proceedings of the IEEK Conference
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    • 2001.06b
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    • pp.237-240
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    • 2001
  • In this paper, we have presented processing technique about wet etching for silicon membrane construction formation. In order to make selective etching of backside silicon wafer, we used Si$_3$N$_4$ layer by PECVD(Plasma Enhanced Chemical Vapor Deposition). We have measured the surface thickness in backside silicon wafer after anisortropic wet etching with KOH:distilled water solutions. Through this experiment, we acquired the etching rate for 1.29${\mu}{\textrm}{m}$/min. The average rough of Si-membrane frontside and backside was 0.26${\mu}{\textrm}{m}$, 0.90${\mu}{\textrm}{m}$, respectively.

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A study on the Fabrication and Characterization of Alumina Electrostatic Chuck for Silicon Wafer Processing (실리콘웨이퍼 공정용 알루미나 정전척의 제작과 특성에 관한 연구)

  • Jeong, Kwang-Jin;Park, Yong-Gyun;Lee, Young-Seop;Cho, Tong-Yul;Chun, Hui-Gon
    • Journal of Sensor Science and Technology
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    • v.8 no.6
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    • pp.481-486
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    • 1999
  • Alumina electrostatic chucks for silicon wafer process with wide range of electrical resistivity were fabricated by controlling the amount of $TiO_2$ addition(0, 1.3, 2.0, 2.8 wt%). The dependence of electrostatic force on applied voltage, temperature and humidity was investigated. In addition, response characteristics on applied voltage and relationship between electrical resistivity and electrostatic force characteristics such as Coulomb force and Johnsen-Rahbeck force were discussed.

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A Real-Time Scheduling System Architecture in Next Generation Wafer Production System (차세대 웨이퍼 생산시스템에서의 실시간 스케줄링 시스템 아키텍처)

  • Lee, Hyun;Hur, Sun;Park, You-Jin;Lee, Gun-Woo;Cho, Yong-Ju
    • Journal of Korean Society of Industrial and Systems Engineering
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    • v.33 no.3
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    • pp.184-191
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    • 2010
  • In the environment of 450mm wafers production known as the next-generation semiconductor production process, one of the most significant features is the full automation over the whole manufacturing processes involved. The full automation system for 450mm wafer production will minimize the human workers' involvement in the manufacturing process as much as possible. In addition, since the importance of an individual wafer processing increases noticeably, it is necessary to develop more robust scheduling systems in the whole manufacturing process than so ever. The scheduling systems for the next-generation semiconductor production processes also should be capable of monitoring individual wafers and collecting useful data on them in real time. Based on the information gathered from these processes, the system should finally have a real-time scheduling functions controlling whole the semiconductor manufacturing processes. In this study, preliminary investigations on the requirements and needed functions for constructing the real time scheduling system and transforming manufacturing environments for 300mm wafers to those of 400mm are conducted and through which the next generation semiconductor processes for efficient scheduling in a clustered production system architecture of the scheduler is proposed. Our scheduling architecture is composed of the modules for real-time scheduling, the clustered production type supporting, the optimal scheduling and so on. The specifications of modules to define the major required functions, capabilities, and the relationship between them are presented.

Fabrication and Chracteristics of Cutting Cell with Various Laser Conditions (다양한 레이저 조건에 따른 컷팅셀 제작 및 특성 분석)

  • Park, Jeong Eun;Kim, Dong Sik;Choi, Won Seok;Jang, Jae Joon;Lim, Dong gun
    • Journal of the Korean Solar Energy Society
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    • v.39 no.3
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    • pp.9-17
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    • 2019
  • Laser cutting cell of solar cells can achieve high voltage and efficiency through more array than conventional 6 inch cell compared to same area. In this study, we fabricated c-Si cutting cell with various lasers and laser conditions such as power, speed, and number of times. In the case of picosecond laser, excellent surface characteristics were obtained due to small surface defects and low thermal damage at the output of 20W and the speed of 100 mm/s. However, it is not possible to fabricate a cutting cell having good characteristics due to nonuniform cutting inside the wafer when the processing for forming a cutting cell is not sufficiently performed. For nanosecond lasers, the best wafer characteristics were obtained for fabrication of excellent cutting cells at a frequency of 500 kHz and a laser speed of 100 mm/s. However, the nanosecond laser has not been processed sufficiently in the condition of a number of times. As a result, it was confirmed that the wafer thickness was cut by $63{\mu}m$ of the cell thickness of $170{\mu}m$ in the condition of five times of laser process. It was found that more than 30% of the wafer thickness had to be processed to fabricate the cutting cell. After cutting the 6-inch cell having the voltage of 0.65 V, we obtained the voltage of about 0.63 V.

In-situ Warpage Measurement Technique Using Impedance Variation (임피던스 변화를 이용한 실시간 기판 변형 측정)

  • Kim, Woo Jae;Shin, Gi Won;Kwon, Hee Tae;On, Bum Soo;Park, Yeon Su;Kim, Ji Hwan;Bang, In Young;Kwon, Gi-Chung
    • Journal of the Semiconductor & Display Technology
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    • v.20 no.1
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    • pp.32-36
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    • 2021
  • The number of processes in the manufacture of semiconductors, displays and solar cells is increasing. And as the processes is performed, multiple layers of films and various patterns are formed on the wafer. At this time, substrate warpage occurs due to the difference in stress between each film and pattern formed on the wafer. the substrate warping phenomenon occurs due to the difference in stress between each film and pattern formed on the wafer. We developed a new warpage measurement method to measure wafer warpage during real-time processing. We performed an experiment to measure the presence and degree of warpage of the substrate in real time during the process by adding only measurement equipment for applying additional electrical signals to the existing ESC and detecting the change of the additional electric signal. The additional electrical measurement signal applied at this time is very small compared to the direct current (DC) power applied to the electrostatic chuck whit a frequency that is not generally used in the process can be selectively used. It was confirmed that the measurement of substrate warpage can be easily separated from other power sources without affecting.