• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2003년도 춘계학술대회 논문집
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• pp.1701-1704
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• 2003

This paper presents a new optimization technique of acceleration curve for a wafer transfer crane movement in which high speed and low vibration are desirable. This technique is based on a genetic algorithm with a penalty function for acceleration optimization under the assumption that an initial profile of acceleration curves constitutes the first generation of the genetic algorithm. Especially the penalty function consists of the violation of constraints and the number of violated constraints. The proposed penalty function makes the convergence rate of optimization process using the genetic algorithm more faster than the case of genetic algorithm without a penalty function. The optimized acceleration of the crane through the genetic algorithm and commercial dynamic analysis software has shown to have accurate movement and low vibration.

• 반도체디스플레이기술학회지
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• 제2권1호
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• pp.25-29
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• 2003

The fluid flow, mass transfer, heat transfer and film thickness variation during the spin coating process are numerically studied. The model is said to be I-dimensional because radial variations in film thickness, concentration and temperature are ignored. The finite difference method is employed to solve the equations that are simplified using the similarity transformation. In early time, the film thinning is due to the radial convective outflow. However that slows during the first seconds of spinning so the film thinning due to evaporation of solvent becomes sole. The time varing film thickness is analyzed according to the wafer spin speed, the various solvent fraction in the coating liquid, and the various solvent vapor fraction in the bulk of the overlying gas during the spin coating is estimated.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2006년도 추계학술발표대회 및 제11회 신소재 심포지엄
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• pp.27.2-27.2
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• 2006

• 산업경영시스템학회지
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• 제38권4호
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• pp.159-167
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• 2015

We consider a wafer lot transfer/release planning problem from semiconductor wafer fabrication facilities to probing facilities with the objective of minimizing the deviation of workload and total tardiness of customers' orders. Due to the complexity of the considered problem, we propose a two-level hierarchical production planning method for the lot transfer problem between two parallel facilities to obtain an executable production plan and schedule. In the higher level, the solution for the reduced mathematical model with Lagrangian relaxation method can be regarded as a coarse good lot transfer/release plan with daily time bucket, and discrete-event simulation is performed to obtain detailed lot processing schedules at the machines with a priority-rule-based scheduling method and the lot transfer/release plan is evaluated in the lower level. To evaluate the performance of the suggested planning method, we provide computational tests on the problems obtained from a set of real data and additional test scenarios in which the several levels of variations are added in the customers' demands. Results of computational tests showed that the proposed lot transfer/planning architecture generates executable plans within acceptable computational time in the real factories and the total tardiness of orders can be reduced more effectively by using more sophisticated lot transfer methods, such as considering the due date and ready times of lots associated the same order with the mathematical formulation. The proposed method may be implemented for the problem of job assignment in back-end process such as the assignment of chips to be tested from assembly facilities to final test facilities. Also, the proposed method can be improved by considering the sequence dependent setup in the probing facilities.

• 제어로봇시스템학회논문지
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• 제5권4호
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• pp.481-488
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• 1999

A thermal model based on the chamber geometry of the industry-standard AST SHS200MA rapid thermal processing system has been developed for the study of thermal uniformity and process repeatability thermal model combines radiation energy transfer directly from the tungsten-halogen lamps and the steady-state thermal conducting equations. Because of the difficulties of solving partial differential equation, calculation of wafer temperature was performed by using finite-difference approximation. The proposed thermal model was verified via titanium silicidation experiments. As a result, we can conclude that the thermal model show good estimation of wafer surface temperature distribution.

• 한국반도체및디스플레이장비학회:학술대회논문집
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• 한국반도체및디스플레이장비학회 2005년도 춘계 학술대회
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• pp.157-162
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• 2005

The wafer's size has been increased up to 300mm according as the devices have been integrated sophisticatedly. For this process to make 300mm-wafer, it is required strict level which removes the particulates on the surface of wafer. Therefore we need new type wet-station which can reduce DI water and chemical in the cleaning process. Moreover, it is very important to control the temperature and the concentration of chemical wet-stat ion. The chemical supply system which is used currently is not only difficult to make a fit mixing rate of chemical in cleaning process, but also it is difficult to make fit quantity and temperature. We propose new chemical supply system, which overcomes the problems via analysis of fluid and thermal transfer on chemical supply system,

• 반도체디스플레이기술학회지
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• 제15권3호
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• pp.72-77
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• 2016

As the semiconductor production technology has gradually developed and intra-market competition has grown fiercer, the caliber of Si Wafer for semiconductor production has increased as well. And semiconductors have become integrated with higher density. Presently the Si Wafer caliber has reached up to 450 mm and relevant production technology has been advanced together. Electrostatic chuck is an important device utilized not only for the Wafer transport and fixation but also for the heat treatment process based on plasma. To effectively control the high calories generated by plasma, it employs a refrigerant-based cooling method. Amid the enlarging Si Wafers and semiconductor device integration, effective temperature control is essential. Therefore, uniformed temperature distribution in the electrostatic chuck is a key factor determining its performance. In this study, the form of refrigerant flow channel will be investigated for uniformed temperature distribution in electrostatic chuck.

• 한국레이저가공학회지
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• 제8권2호
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• pp.7-12
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• 2005

The material processing of UV nanosecond pulse laser cannot be avoided the material shape change and contamination caused by interaction of base material and laser beam. Nowadays, ultra short pulse laser shorter than nanosecond pulse duration is used to overcome this problem. The advantages of this laser are no heat transfer, no splashing material, no left material to the adjacent material. Because of these characteristics, it is so suitable for micro material processing. The processing of sapphire wafer was done by UV 355nm, green 532nm, IR 1064nm. X-Y motorized stage is installed to investigate the proper laser beam irradiation speed and cycles. Also, laser beam fluence and peak power are calculated.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2000년도 Proceedings of 5th International Joint Symposium on Microeletronics and Packaging
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• pp.57-64
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• 2000

As integrated circuits become more complex, the number of I/O connections per chip grow. Conventional wire-bonding, lead-frame mounting techniques are unable to keep up. The space saved by shrinking die size is lost when the die is packaged in a huge device with hundreds of leads. The solution is bumps; gold, conductive adhesive, but most importantly solder bumps. Virtually every semiconductor manufacturer in the world is using or planning to use bump technology fur their larger and more complex devices. Several wafer-bumping processes used in the manufacture of bumped wafer. Some of the more popular techniques are evaporative, stencil or screen printing, electroplating, electrodes nickel, solder jetting, stud bumping, decal transfer, punch and die, solder injection or extrusion, tacky dot process and ball placement. This paper will discuss the process steps for bumping wafers using these techniques. Critical cleaning is a requirement for each of these processes. Key contaminants that require removal are photoresist and flux residue. Removal of these contaminants requires wet processes, which will not attack, wafer metallization or passivation. research has focused on enhanced cleaning solutions that meet this critical cleaning requirement. Process parameters defining time, temperature, solvency and impingement energy required to solvate and remove residues from bumped wafers will be presented herein.

• 마이크로전자및패키징학회지
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• 제7권1호
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• pp.51-59
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• 2000

As integrated circuits become more complex, the number of I/O connections per chip grow. Conventional wire-bonding, lead-frame mounting techniques are unable to keep up. The space saved by shrinking die size is lost when the die is packaged in a huge device with hundreds of leads. The solution is bumps; gold, conductive adhesive, but most importantly solder bumps. Virtually every semiconductor manufacturer in the world is using or planning to use bump technology for their larger and more complex devices. Several wafer-bumping processes used in the manufacture of bumped wafer. Some of the more popular techniques are evaporative, stencil or screen printing, electroplating, electroless nickel, solder jetting, stud humping, decal transfer, punch and die, solder injection or extrusion, tacky dot process and ball placement. This paper will discuss the process steps for bumping wafers using these techniques. Critical cleaning is a requirement for each of these processes. Key contaminants that require removal are photoresist and flux residue. Removal of these contaminants requires wet processes, which will not attack, wafer metallization or passivation. Research has focused on enhanced cleaning solutions that meet this critical cleaning requirement. Process parameters defining time, temperature, solvency and impingement energy required to solvate and remove residues from bumped wafers will be presented herein.