• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.06a
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• pp.1-5
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• 2005

The grinding process is replacing lapping and etching process because significant cost savings and performance improvemnets is possible. This paper presents the experimental results of wafer grinding. A three-variable two-level full factorial design was employed to reveal the main effects as well as the interaction effects of three process parameters such as wheel rotational speed, chuck table rotational speed and feed rate on TTV and STIR of wafers. The chuck table rotaional speed was a significant factor and the interaction effects was significant. The ground wafer shape was affected by surface shape of chuck table.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.33 no.9
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• pp.969-975
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• 2009

In this paper, bonded wafer analysis system is proposed using laser beam transmission; while the transmission model is derived by simulation. Since the failure of bonded wafer stems in void existence, transmittance deviations caused by the thickness of the void are analyzed and variations of the intensity through the void or defect easily have been recognized then the testing power has been increased. In addition, large screen display on laser study has been done which resulted in acquiring a feasible technique for analysis of the whole bonding surface. In this regard, three approaches are demonstrated in which Halogen lamp, IR lamp and laser have been tested and subsequently by results comparison the optimized technique using laser has been derived.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2004.04a
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• pp.149-152
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• 2004

Generally the wafer is increased by 300mm. We are desired that the wafer is prevented from pollutions of metal contaminant on surface of wafer. We have to develop new wafer cleaning process of IC Manufacturing that can reduce DI water and chemical by removal of the wafer cleaning process step. Moreover, it is difficult to control temprature and density of chemical in spite of rapidly increasing automation of system. We design smart module controller for new generation of semiconductor wet station with intelligent algorithm using data that is taken by computer simulation for optimal system.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2000.05a
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• pp.854-857
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• 2000

Chemical Mechanical Polishing(CMP) has been accepted as one of the essential processes for VLSI fabrication. However, as the polishing process continues, pad pores get to be glazed by polishing residues, which hinder the supply of new slurry. This defect makes removal rate decrease with a number of polished wafer and the desired within-chip planarity, within wafer and wafer-to-wafer nonuniformity are unable to be achieved. So, pad conditioning is essential to overcome this defect. The eletroplated diamond grit disk is used as the conventional conditioner, And alumina long fiber, the .jet power of high pressure deionized water and vacuum compression are under investigation. But, these methods have the defects like scratches on wafer surface by out of diamond grits, subsidences of pad pores by over-conditioning, and the limits of conditioning effect. To improve these conditioning methods. this paper presents the Characteristics of Ultrasonic conditioning aided by cavitation.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.152-152
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• 2014

최근 반도체의 고집적화로 high dose implant 도입과 소자의 동작 특성 향상을 위한 low-k 물질 도입에 따라 다양한 주변 공정의 변화를 이끌고 있다. 이에 따라 반도체 제조의 핵심 공정 단계 중 하나인 ashing 단계에서 기존 성능 이상의 장비를 기대하고 있으며, 그것을 평가하기 위한 중요 요소로 uniformity와 fast stripping이 있다. 본 연구에서는 유체해석 시뮬레이션을 통해 450 mm ashing 챔버에서의 gas inlet baffle과 wafer stage 사이의 최적 거리를 예측했다. 우선적으로 시뮬레이션의 신뢰도를 높이기 위해 실험으로 측정한 300 mm ashing 결과와 유체해석 결과 molecular flux의 상관관계를 파악하여, 450 mm ashing 챔버의 최적 구조를 예측하였다. 선행 연구한 300 mm 시뮬레이션 결과를 바탕으로 이상적인 450 mm ashing 챔버를 설계하였다. 유체해석 결과는 동일한 형태의 수직형 구조 장비에서 baffle과 wafer stage 사이의 거리가 35 mm에서 60 mm일 때, 450 mm wafer surface 위에서 더욱 균일한 density 분포를 나타내었다. Reactant flux 분포는 거리가 60 mm에서 80 mm 사이일 경우 더 균일하게 나타났다. 그러므로, 450 mm 챔버에서 gas inlet baffle과 wafer stage 간격이 60 mm일 때 최적의 구조로 판단된다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.2
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• pp.114-118
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• 2009

PVA (polyvinyl alcohol) brush cleaning method is a typical cleaning method for semiconductor cleaning process especially post-CMP cleaning. PVA brush contacts with the wafer surface and abrasive particle, generating the contact rotational torque of the brush, which is the removal mechanism. The brush rotational torque can overcome theoretically the adhesion force generated between the abrasive particle and wafer by zeta potential. However, after CMP (chemical mechanical polishing) process, many particles remained on the wafer because the brush was contaminated in previous post-CMP cleaning step. The abrasive particle on the brush redeposits to the wafer. The level of the brush contamination increased according to the cleaning run time. After cleaning the brush, the level of wafer contamination dramatically decreased. Therefore, the brush cleanliness effect on the cleaning performance and it is important for the brush to be maintained clearly.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2012.10a
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• pp.621-622
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• 2012

• Journal of Sensor Science and Technology
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• v.15 no.5
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• pp.341-346
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• 2006

We have fabricated SOI CMOS active pixel image sensor with the pinned photodiode on handle wafer in order to reduce dark currents and improve spectral response. The structure of the active pixel image sensor is 4 transistors APS which consists of a reset and source follower transistor on seed wafer, and is comprised of the photodiode, transfer gate, and floating diffusion on handle wafer. The source of dark current caused by the interface traps located on the surface of a photodiode is able to be eliminated, as we apply the pinned photodiode. The source of dark currents between shallow trench isolation and the depletion region of a photodiode can be also eliminated by the planner process of the hybrid bulk/SOI structure. The photodiode could be optimized for better spectral response because the process of a photodiode on handle wafer is independent of that of transistors on seed wafer. The dark current was about 6 pA at 3.3 V of floating diffusion voltage in the case of transfer gate TX = 0 V and TX=3.3 V, respectively. The spectral response of the pinned photodiode was observed flat in the wavelength range from green to red.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2006.05a
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• pp.555-556
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• 2006

In recent years, the higher flatness level in wafer shape has been strictly demanded with a high integration of the semiconductor devices. It has become difficult for a conventional wafer preparing process to satisfy those demands. In order to meet those demands, surface grinding with in-feed grinder is adopted. In an in-feed grinding method, a chuck table fur fixing a semiconductor wafrr rotates on its rotation axis with a slight tilt angle to the rotation axis of a cup shaped grinding wheel and the grinding wheel in rotation moves down to grind the wafer. So, stability of the grinder structure is very important to aquire a wafer of good quality. This paper describes the features of the in-feed grinder and some FEM analysis results of the grinder structure.

• Journal of Institute of Control, Robotics and Systems
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• v.5 no.4
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• pp.481-488
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• 1999

A thermal model based on the chamber geometry of the industry-standard AST SHS200MA rapid thermal processing system has been developed for the study of thermal uniformity and process repeatability thermal model combines radiation energy transfer directly from the tungsten-halogen lamps and the steady-state thermal conducting equations. Because of the difficulties of solving partial differential equation, calculation of wafer temperature was performed by using finite-difference approximation. The proposed thermal model was verified via titanium silicidation experiments. As a result, we can conclude that the thermal model show good estimation of wafer surface temperature distribution.