• 센서학회지
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• 제22권1호
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• pp.89-94
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• 2013

In this paper, we developed a beam of MEMS probe card using a BeCu sheet. Silicon wafer thickness of $400{\mu}m$ was fabricated by using deep reactive ion etching (RIE) process. After forming through silicon via (TSV), the silicon wafer was bonded with BeCu sheet by soldering process. We made BeCu beam stress-free owing to removing internal stress by using joule heating. BeCu beam was fused by using joule heating caused by high current. The fabricated BeCu beam measured length of 1.75 mm and width of 0.44 mm, and thickness of $15{\mu}m$. We measured fusing current as a function of the cutting planes. Maximum current was 5.98 A at cutting plane of $150{\mu}m^2$. The proposed low-cost and simple fabrication process is applicable for producing MEMS probe beam.

• Journal of Electrical Engineering and Technology
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• 제10권1호
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• pp.325-330
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• 2015

With approval from the Asia Pacific Metrology Program Working Group on Materials Metrology (APMP WGMM), an international comparison for sheet resistance standards for silicon wafers was firstly conducted among Korea Research Institute of Standards and Science (KRISS) in Korea, CMS/ITRI in Taiwan, and NIM in China, which are national metrology institutes (NMIs), from August 2011 to January 2012. The sheet resistance values of the standards are $10{\Omega}$, $100{\Omega}$, and $1000{\Omega}$; the measurement was conducted in sequence at KRISS, CMS/ITRI, NIM, and KRISS again using the four-point probe method with single and dual configuration techniques. The reference value for the measurement results of the three NMIs was obtained through averaging the values of the three results for each sheet resistance range. The differences between the reference value and the measured values is within 0.22% for $10{\Omega}$, 0.17% for $100{\Omega}$, and 0.12% for $1000{\Omega}$. Therefore, the international consistency for conducting sheet resistance measurements is confirmed within 0.22% through the APMP WGMM approved comparison.

• 한국정밀공학회지
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• 제17권5호
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• pp.70-75
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• 2000

After the patterning and probe process of wafer have been achieved, the dicing process is necessary to separate chips from a wafer. The dicing process cuts a wafer to lengthwise and crosswise direction to make many chips by using narrow circular rotating diamond blade. But inferior goods are made under the influence of complex dicing environment such as blade, wafer, cutting water and cutting conditions. This paper describes a monitoring algorithm using feature extraction in order to find out an instant of vibration signal change when bad dicing appears. The algorithm is composed of two steps: feature extraction and decision. In the feature extraction, two features processed from vibration signal which is acquired by accelerometer attached on blade head are proposed. In the decision. a threshold method is adopted to classify the dicing process into normal and abnormal dicing. Experiment have been performed for GaAs semiconductor wafer. Based upon observation of the experimental results, the proposed scheme shown a good accuracy of classification performance by which the inferior goods decreased from 35.2% to 12.8%.

• Journal of Electrical Engineering and Technology
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• 제6권1호
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• pp.119-122
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• 2011

A new high speed AFM probe has been proposed and fabricated. The probe is integrated with PZT actuated cantilever realized in bulk silicon wafer using heavily boron doped silicon as an etch stop layer. The cantilever thickness can be accurately controlled by the boron diffusion process. Thick SCS cantilever and integrated PZT actuator make it possible to be operated at high speed for fast imaging. The resonant frequency of the fabricated probe is 92.9 kHz and the maximum deflection is 5.3 ${\mu}m$ at 3 V. The fabricated probe successfully measured the surface of standard sample in an AFM system at the scan speed of 600${\mu}m$/sec.

• 한국정밀공학회지
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• 제18권2호
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• pp.111-118
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• 2001

Tungsten probe is the most important part of a probe card, which is widely used for the performance test of wafer chips. Electro chemical etching becomes an exclusive choice for mass production of the tungsten probes. In the mass production, not only the shape of the probe but also the shape distribution of machined probes is important. A new method is proposed for the mass production of the tungsten probes. Tungsten wires are separated by a distance, and dipped into electrolyte. The dipping rate is controlled to shape the probes. Several experimental tests are performed to study the machining characteristics. From the test results, machining parameters including electrical conditions and anode position showed significant influences on the shape, repeatability, precision and quality of sharp tips.

• JSTS:Journal of Semiconductor Technology and Science
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• 제1권1호
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• pp.15-19
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• 2001

Current leakage is the major failure mode of semiconductor device characteristic failures. Conventionally, failures such as short circuit breaks and gate breakdowns have been analyzed and the detected causes have been reflected in the fabrication process. By using a wafer-level emission-leakage failure analysis method (in-line QC), we analyzed leakage mode failure, which is the major failure detected during the probe inspection process for LSIs, typically DRAMs and CMOS logic LSIs. We have thus developed a new technique that copes with the critical structural failures and random failures that directly affect probe yields.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2003년도 추계학술대회
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• pp.1448-1452
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• 2003

A scratch tester was developed to evaluate the adhesive strength at interface between thin-film and substrate(silicon wafer). Under force control, the scratch tester can measure the normal and the tangential forces simultaneously as the probe tip of the equipment approaches to the interface between thin-film and substrate of wafer. The capacity of each component of force sensor is 0.1 N ${\sim}$ 100 N. In addition, the tester can detect the signal of elastic wave from AE sensor(frequency range of 900 kHz) attached to the probe tip and evaluate the bonding strength of interface. Using the developed scratch tester, the feasibility test was performed to evaluate the adhesive strength of thin-film.

• 한국정밀공학회지
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• 제23권7호
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• pp.138-145
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• 2006

A nanopatterning technique was proposed and demonstrated for low cost and mass productive process using the scanning probe lithography (SPL) and soft lithography. The nanometer scale structure is fabricated by the localized generation of oxide patterning on the H-passivated (100) silicon wafer, and soft lithography was performed to replicate of nanometer scale structures. Both height and width of the silicon oxidation is linear with the applied voltagein SPL, but the growth of width is more sensitive than that of height. The structure below 100 nm was fabricated using HF treatment. To overcome the structure height limitation, aqueous KOH orientation-dependent etching was performed on the H-passivated (100) silicon wafer. Soft lithography is also performed for the master replication process. Elastomeric stamp is fabricated by the replica molding technique with ultrasonic vibration. We showed that the elastomeric stamp with the depth of 60 nm and the width of 428 nm was acquired using the original master by SPL process.

• 한국재료학회지
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• 제23권6호
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• pp.316-321
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• 2013

The electrical properties and surface morphology changes of a silicon wafer as a function of the HF concentration as the wafer is etched were studied. The HF concentrations were 28, 30, 32, 34, and 36 wt%. The surface morphology changes of the silicon wafer were measured by an SEM ($80^{\circ}$ tilted at ${\times}200$) and the resistivity was measured by assessing the surface resistance using a four-point probe method. The etching rate increased as the HF concentration increased. The maximum etching rate 27.31 ${\mu}m/min$ was achieved at an HF concentration of 36 wt%. A concave wave formed on the wafer after the wet etching process. The size of the wave was largest and the resistivity reached 7.54 $ohm{\cdot}cm$ at an 30 wt% of HF concentration. At an HF concentration of 30 wt%, therefore, a silicon wafer should have good joining strength with a metal backing as well as good electrical properties.

• 한국전자파학회논문지
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• 제30권2호
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• pp.111-123
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• 2019

본 논문에서는 온-웨이퍼형 DUT 측정을 위한 입력 터미네이션의 정의방법을 제안하였으며, 제안된 방법으로 새롭게 정의된 입력 터미네이션과 잡음전력비에 기초한 잡음상관행렬 측정방법을 이용, 온-웨이퍼형 DUT의 잡음상관행렬을 측정하였다. 그리고 온-웨이퍼 DUT를 측정하기 위해 웨이퍼 프로브와 바이어스-티가 포함된 잡음측정 구성을 보였다. 온-웨이퍼형 DUT 측정을 위한 입력 터미네이션을 정의하기 위해서는 바이어스-티와 프로브 그리고 open으로 종단된 선로가 결합된 어댑터의 S-파라미터가 필요하며, 이를 위해 1-포트 측정을 통해 어댑터의 2-포트 S-파라미터를 결정하는 방법을 보였다. 이 측정된 어댑터의 S-파라미터 이용, 온-웨이퍼형 DUT 측정을 위한 새로운 입력 터미네이션을 정의하는 방법을 보였다. 제안된 방법으로 1.5 dB의 잡음지수를 갖는 칩 소자의 잡음상관행렬을 측정하였고, 측정된 잡음상관행렬을 이용하여 칩 소자의 잡음 파라미터 결과를 얻었다. 칩 소자의 잡음 파라미터 결과는 칩 소자의 데이터시트에 있는 잡음 파라미터 결과와 유사한 결과를 보였으며, 반복 측정을 통해 측정된 결과가 신뢰할 수 있는 결과임을 보였다.