• 제목/요약/키워드: Volume of the building

검색결과 816건 처리시간 0.026초

현대건축물 표피의 내.외부 공간 표현성 변화에 관한 연구 (Study on Changes of Physical Expression in Interior and Exterior Surfaces in Contemporary Architecture)

  • 이일표;박현수
    • 한국실내디자인학회:학술대회논문집
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    • 한국실내디자인학회 2006년도 춘계학술발표대회 논문집
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    • pp.131-134
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    • 2006
  • This study aims to inspect changes of physical expression in surfaces of both building interior and exterior in contemporary architecture. Nowadays society has transformed into more complicated framework with the development of the new media and digital technology in 21 century. Surface's expressivity has been changed with design trend and material development. Although surface study has been mainly concentrated on properties of materials and structure characters, new technology and cultural acceptance enables it extend itself to a new area with various design methods, taking its place as an important contemporary architectural element. Interior surface design is expressed with several unique methods such as optical illusion, surface exposure and spacial depth and volume, and it created dynamic space within the surface itself. In case of exterior surface, whole space seems to be designed to be coordinated with structured optical illusion as well as symbolic expression. Surface's area is extends itself with the stream of the times. This study explored the nature of surfaces with categorizing and comparing them in a various views and methods.

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창원시 학교 건축물의 냉난방부하에 대한 전력 소비량 추정에 관한 연구 (A Study on Prediction of Power Consumption Rate for Heating and Cooling load of School Building in Changwon City)

  • 박효석;최정민;조성우
    • 교육녹색환경연구
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    • 제11권2호
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    • pp.19-27
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    • 2012
  • This study was carried out in order to establish the estimation equation for school power consumption using regression analysis based on collected power consumption for two years of weather data and schools are located in Central Changwon and Masan district in Changwon city. (1) The power consumption estimation equation for Heating and cooling is calculated using power consumption per unit volume, the difference between actual power consumption and results of estimation equations is 4.1%. (2) The power consumption estimation equation for heating load is showed 2.6% difference compared to actual power consumption in Central Changwon and is expressed 2.9% difference compared to that in Masan district. Therefore, the power consumption prediction for each school using the power consumption estimation equation is possible. (3) The power consumption estimation equation for cooling load is showed 8.0% difference compared to actual power consumption in Central Changwon and is expressed 2.9% compared to that in Masan district. As the power consumption estimation equation for cooling load is expressed difference compared to heating load, it needs to investigate influence for cooling load.

기존 학교건물 골조와 내진보강요소 일체화를 위한 변형경화형 시멘트 복합체를 적용한 스터드 전단 접합부의 구조성능 (Structural Performance of Stud Shear Connections using SHCC between Existing School Building Frame and Seismic Retrofitting Elements)

  • 김성호;윤현도
    • 교육시설 논문지
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    • 제20권4호
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    • pp.35-43
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    • 2013
  • Some results of experimental investigation conducted to assess the effect of cement composite strength and ductility on the shear behavior and crack-damage mitigation of stud connections between existing reinforced concrete frame in school buildings and seismic strengthening elements from cyclically direct shear tests are described. The cement composite strengths include 50 for medium strength and 70 MPa for high strength. Two types of cement composites, strain-hardening cement composite (SHCC) and non-shrinkage mortar, are used for stud shear connection specimens. The special SHCCs are reinforced with hybrid 0.2% polyethylene (PE) and 1.3% polyvinyl alcohol (PVA) fibers at the volume fraction and exhibits tensile strain capacity ranging from 0.2 to 0.5%. Test result indicates that SHCC improves the seismic performance and crack-damage mitigation of stud shear connections compared with stud connections with non-shrinkage mortar. However, the performance enhancement in SHCC stud connections with transverse and longitudinal reinforcements is less notable for those without additional reinforcement.

대규모 건물의 기밀성능 측정기준 수립에 관한 연구 (Study on the Establishment of Large Building Airtightness Measurement Standards)

  • 이동석;지경환;조재훈
    • 한국태양에너지학회 논문집
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    • 제34권1호
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    • pp.117-124
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    • 2014
  • Airtightness standards using fan pressurization method are normally used for measuring small buildings, detached houses, and apartment units. And, it is easy to conduct airtightness measurement through this fan pressurization method. However, it can be difficult to achieve accurate measurement results for the large buildings as the height and volume of the buildings have been increased. In this paper, we studied the principle of airtightness method by fan pressurization. And, we reviewed the measurement process described in ISO 9972, EN 13829, ASTM E779, ATTMA TS 1, CAN/CGSB 149.15, and JIS A 2201. Then, we categorized the methods' items according by air flow rate (Q) and pressure difference(${\Delta}P$). As a result, we made a comparison analysis on the measurement methods appeared in each standards. And, we achieved 5 test conditions about air flow rate and pressure difference to state requirements for large buildings airtightness measurement.

폐타이어 분말과 난연제가 혼입된 모르타르의 화재안전에 관한 연구 (Research on Fire Safety of Mortar-Containing Waste Tire Powders and Flame Retardant)

  • 박정진;손기상
    • 한국화재소방학회논문지
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    • 제24권4호
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    • pp.12-17
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    • 2010
  • 본 연구는 자원의 재활용 측면에서 적용한 폐타이어 분말을 혼입한 모르타르에 난연제를 첨가하여 그 난연특성을 알아보고자 한다. 폐타이어 분말의 혼입으로 단열성능 향상은 이미 검증이 되었으나, 단열성과 결합력의 상반된 재료 특성으로 인해 화재에는 취약한 바. 이에 난연제를 첨가하여 인명안전에 만전을 기하고자 한다. 폐타이어 분말을 혼입한 모르타르의 난연제를 첨가하여 첨가 비율에 따른 그 특성을 알아보고자 한다. 화재 초기의 특성을 알 수 있는 재료의 가연성 여부를 실제 화재와 유사한 복사열에 의해 시험하고자 하였으며. 실험방법은 한국건자재 시험연구원에 의뢰하여 ISO 5657 절차에 의한 재료의 착화시간, 불꽃 발생여부, 시험체의 형태변화 등을 고찰하고자 한다. 폐타이어 분말이 혼입된 모르타르와 난연제(무기계)의 배합비율은 폐타이어 분말의 0%, 30%, 60%, 90% 비율로 수산화알루미늄을 첨가하며 조연제인 삼산화안티몬은 난연제의 10%를 첨가한다. 시험체를 수평설치하여 일정한 복사열($1{\sim}5W/cm^2$)을 시험체 상부표면에 노출시키면 열이 시험체 표면에서 내부로 전도되어 온도가 상승한다. 온도가 충분히 높다면 시험체는 열분해하면서 가연성가스를 발생시킨다. 이 때 점화원인 점화기구의 작은 불꽃은 시험체 중앙 위의 10mm 지점에 규칙적인 간격으로 접염하였을때의 재료의 지속적인 표면 착화특성(착화시간) 평가한다. 난연제 미첨가시에도 착화가 일어나지 않아 폐타이어분말이 혼입된 모르타르의 가연성은 적은 것으로 볼 수 있으며, 화재실내에 존재하는 가연물의 양을 평가하는 화재하중에 이를 반영할 수 있다. 폐타이어 분말에 무기계 난연제를 첨가함에 따라 흡열효과에 의해 불꽃은 발생하지 아니하고 폐타이어 분말입자의 분해속도도 지연되었음을 확인할 수 있다. 복사열로 인해 난연제인 수산화알루미늄이 열분해하여 모르타르내 수증기 분압이 증가하여, 폐타이어 분말의 불꽃이나 연소형태는 보이지 않았다.

효율적인 BCC 볼륨 데이터의 GPU 등가면 광선투사법 (Efficient GPU Isosurface Ray-casting of BCC Datasets)

  • 김민호;김현준
    • 한국컴퓨터그래픽스학회논문지
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    • 제19권2호
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    • pp.19-27
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    • 2013
  • 본 연구에서는, 결과물의 우수함을 유지하면서도 기존 연구결과의 성능을 4-7배 향상시킨 실시간 GPU 등가면 볼륨 레이케스터를 제시한다. 이러한 성능 향상은 효율적인 빈공간 생략법과 분석적 그레디언트 계산법을 도입함으로써 가능하다. 빈공간 생략법은 스플라인 조각들의 BB-형식으로부터 만등어진 최소/최대값 옥트리에 기반하고 있고, 분석적 그레디언트 계산법은 보다 정확한 렌더링 결과를 제공할 뿐 아니라 더욱 빠른 계산이 가능하도록 한다.

쾌속조형의 속도를 향상시키기 위한 알고리즘 (An Algorithm to Speed Up the Rapid Prototyping)

  • 고민석;장민호;왕지남;박상철
    • 한국정밀공학회지
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    • 제25권3호
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    • pp.157-164
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    • 2008
  • While developing physical prototype from CAD model, rapid prototyping mainly focuses on two key points reducing time and material consumption. So, we have to change from a traditional solid model to building a hollowed prototype. In this paper, a new method is presented to hollow out solid objects with uniform wall thickness to increase RP efficiency. To achieve uniform wall thickness, it is necessary to generate internal contour by slicing the offset model of an STL model. Due to many difficulties in this method, this paper proposes a new algorithm that computes internal contours computing offset model which is generated from external contour using wall thickness. Proposed method can easily compute the internal contour by slicing the offset surface defined by the sum of circle swept volumes of external contours without actual offset and the circle wept volumes. Internal contour existences are confirmed by using the external point. Presented algorithm uses the 2D geometric algorithm allowing RP implementation more efficient. Various examples have been tested with implementation of the algorithm, and some examples are presented for illustration.

Development of the Camera System for Total Solar Eclipse

  • Kim, Jihun;Choi, Seonghwan;Park, Jongyeob;Bong, Su-Chan;Jang, Bi-Ho;Park, Sung-Joon;Yang, Heesu;Park, Young-Deuk;Cho, Kyungsuk
    • 천문학회보
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    • 제42권2호
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    • pp.84.3-85
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    • 2017
  • Korea Astronomy and Space Science Institute (KASI) has been developing the Camera System for the Total Solar Eclipse (TSE) observation. In 2016 we have assembled a simple camera system consisting of a commercial camera lens, a polarizer, bandpass filters, and a Canon camera to observe the solar corona during the Total Solar Eclipse in Indonesia. For 2017 TSE observation, we have studied and adapted the compact coronagraph design proposed by NASA. The compact coronagraph design dramatically reduces the volume and weight, and used for TSE observation. The camera is used to test and verify key components including function of bandpass filter, polarizer, and CCD during observing the Total Solar Eclipse. In this poster we focus on optical engineering works including designing, analyzing, testing, and building for the TSE observation.

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GSIS를 이용한 도로종합정보관리 시스템 구축 (Building of Road Information Management System using GSIS)

  • 정승현;임승현;조기성
    • 한국측량학회지
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    • 제16권2호
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    • pp.169-176
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    • 1998
  • 최근 급속한 사회발전과 지역간의 인적ㆍ물적 교류의 증가로 교통량이 급증하고 있으며, 이로 인해 기존 도로에 대한 유지 및 관리의 중요성이 크게 대두되고 있다. 따라서 본 연구는 일반국도를 대상으로 과학적이고 효율적인 도로의 유지, 관리업무를 위한 시범적인 도로종합정보관리 시스템을 구축하는데 목적이 있다. 지형공간정보체계를 이용하여 기존 도로에 대한 도면 및 대장과 조서상의 각종 정보를 수치화 및 데이터베이스화함으로서, 도면의 자동화는 물론 도로 제반 시설물의 검색, 갱신 및 통계분석 기능을 통해 도로의 유지보수 및 관리 업무시 신속하고 정확한 정보를 제공할 수 있도록 하였다.

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Through Silicon Stack (TSS) Assembly for Wide IO Memory to Logic Devices Integration and Its Signal Integrity Challenges

  • Shin, Jaemin;Kim, Dong Wook
    • 한국전자파학회지:전자파기술
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    • 제24권2호
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    • pp.51-57
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    • 2013
  • The current expanding mobile markets incessantly demands small form factor, low power consumption and high aggregate throughput for silicon-level integration such as memory to logic system. One of emerging solution for meeting this high market demand is 3D through silicon stacking (TSS) technology. Main challenges to bring 3D TSS technology to the volume production level are establishing a cost effective supply chain and building a reliable manufacturing processes. In addition, this technology inherently help increase number of IOs and shorten interconnect length. With those benefits, however, potential signal and power integrity risks are also elevated; increase in PDN inductance, channel loss on substrate, crosstalk and parasitic capacitance. This paper will report recent progress of wide IO memory to high count TSV logic device assembly development work. 28 nm node TSV test vehicles were fabricated by the foundry and assembled. Successful integration of memory wide IO chip with less than a millimeter package thickness form factor was achieved. For this successful integration, we discussed potential signal and power integrity challenges. This report demonstrated functional wide IO memory to 28 nm logic device assembly using 3D package architecture with such a thin form factor.