• International journal of advanced smart convergence
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• v.10 no.1
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• pp.12-23
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• 2021

This paper proposes a low power radio frequency receiver front-end where, in a single stage, single-balanced mixer and voltage-controlled oscillator are stacked on top of low noise amplifier and re-use the dc current to reduce the power consumption. In the proposed topology, the voltage-controlled oscillator itself plays the dual role of oscillator and mixer by exploiting a series inductor-capacitor network. Using a 65 nm complementary metal oxide semiconductor technology, the proposed radio frequency front-end is designed and simulated. Oscillating at around 2.4 GHz frequency band, the voltage-controlled oscillator of the proposed radio frequency front-end achieves the phase noise of -72 dBc/Hz, -93 dBc/Hz, and -113 dBc/Hz at 10KHz, 100KHz, and 1 MHz offset frequency, respectively. The simulated voltage conversion gain is about 25 dB. The double-side band noise figure is -14.2 dB, -8.8 dB, and -7.3 dB at 100 KHz, 1 MHz and 10 MHz offset. The radio frequency front-end consumes only 96 ㎼ dc power from a 1-V supply.

• Journal of Advanced Marine Engineering and Technology
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• v.33 no.5
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• pp.756-761
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• 2009

In this paper, a X band voltage controlled oscillator is proposed. The oscillator uses a transistor as an oscillating element and its oscillating frequencies are controlled by the tuning voltage of varactor diode. Using the circuit simulation tools, the matching circuits between the transistor and varactor diode, its input and output matching circuits, and a feedback circuits are designed. The measured results of the fabricated oscillator show that its oscillation frequencies are from 10.50GHz to 10.88GHz according to the turning voltages of 1V to 18V, its output power levels are about 4.3dBm, and its phase noise is around -43.5dBc/Hz at 100kHz offset frequency of 10.5GHz.

• Journal of Multimedia Information System
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• v.5 no.2
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• pp.139-142
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• 2018

This work presents a novel architecture of phase locked loop (PLL) with the current compensating scheme to improve phase noise characteristic. The proposed PLL has two charge pumps (CP), main-CP (MCP) and sub-CP (SCP). The smaller SCP current with same time duration but opposite direction of UP/DN MCP current is injected to the loop filter (LF). It suppresses the voltage fluctuation of LF. The PLL has a novel voltage controlled oscillator (VCO) consisting of a voltage controlled resistor (VCR) and the three-stage ring oscillator with latch type delay cells. The VCR linearly converts voltage into current, and the latch type delay cell has short active on-time of transistors. As a result, it improves phase noise characteristic. The proposed PLL has been fabricated with $0.35{\mu}m$ 3.3 V CMOS process. Measured phase noise at 1 MHz offset is -103 dBc/Hz resulting in 3 dBc/Hz phase noise improvement compared to the conventional PLL.

• Journal of Sensor Science and Technology
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• v.28 no.2
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• pp.121-126
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• 2019

The voltage-controlled oscillator is one of the fundamental building blocks that determine the signal quality and power consumption in RF transceivers for wireless sensor networks. Ring oscillators are attractive owing to their small form factor and multi-phase capability despite the relatively poor phase noise performance in comparison with LC oscillators. The phase noise of a ring oscillator can be improved by using a coupled structure that works at a lower frequency. This paper introduces a 2.4 GHz low-noise ring oscillator that consists of two 3-stage coupled ring oscillators. Each sub-oscillator operates at 800 MHz, and the multi-phase signals are combined to generate a 2.4 GHz quadrature output. The voltage-controlled ring oscillator designed in a 65-nm standard CMOS technology has a tuning range of 800 MHz and exhibits the phase noise of -104 dBc/Hz at 1 MHz offset. The power consumption is 13.3 mW from a 1.2 V supply voltage.

• 한국정보통신설비학회:학술대회논문집
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• 2008.08a
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• pp.441-446
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• 2008

In this papers, a PLDRO(Phase Locked Dielectric Resonator Oscillator) is designed and implemented at the oscillator in which fundamental frequency is 18.3 GHz. The proposed PLDRO so as to improve the PLDRO of the general structure is designed to the goal of the minimize of the size and the performance improvement. Three VCO(Voltage controlled Oscillator) and the power combiner improved the output power. A VCDRO(Voltage Controlled Dielectric Resonator Oscillator) is manufactured using a varactor diode to tune oscillating frequency electrically, and its phase is locked to reference frequency by SPD(Sampling Phase Detector). This product is fabricated on Teflon substrate with dielectric constant 2.2 and device is ATF -13786 of Ka-band using. This PLDRO generates an output power of 5.67 dBm at 18.3 GHz and has the characteristics of a phase noise of -80.10 dBc/Hz at 1 kHz offset frequency from carrier, the second harmonic suppression of -33 dBc. The proposed PLDRO can be used in Ka-band satellite applications

• Journal of information and communication convergence engineering
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• v.8 no.5
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• pp.566-569
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• 2010

This paper describes the sinusoidal, pulse, triangular oscillator using second generation current conveyor. To obtain the sinusoidal waveform the circuit blocks are constructed by using all pass filter and integrator. The pulse and the triangular waveforms are obtained from the output of sinusoidal oscillator. The peak-to-peak voltages of sinusoidal and triangular waveforms can be easily controlled by the dc offset voltage. Also the output frequency of the oscillator can be controlled by varying passive elements. The designed circuit is verified by HSPICE simulation.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.605-606
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• 2006

Voltage Controlled Oscillator(VCO) plays an important role in today's communication systems. Especially, a Clock Generator(CG) in phase-locked loop(PLL) is usually realized by the VCO. This paper proposes a new VCO with a controllable duty cycle buffer, that can be adopted in low-power high-speed communication systems. Delay cell of the VCO is implemented with gilbert cell. Frequency dynamic range of the VCO is in the range of approximately $50MHz{\sim}500MHz$. Parameters with N-well CMOS 0.18-um process with 1.8V supply voltage was used for the simulations.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.1
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• pp.61-64
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• 2001

VCO(Voltage Contolled Oscillator) is one of the main components governing the size, performance and power consumption of telecommunication devices. As the devices become much smaller, YCO need to hove much smaller size with better characteristics. Buried type passive components of L, C, R were developed previously and the structure of these components are good for minimizing the size of VCO. Our own library of passive components is used in simulation and measurement circuit designed by ourselve. In structure of multi-layered VCO, some components governing the characteristics of VCO are selected and placed on the top of oscilltor for the good tuning process. In resonator part, the stripline structure and low loss glass/ceramic material are used to get higher Q value. In our research, a VCO oscillates in the 2.3~2.36 GHz band is developed.

• Journal of information and communication convergence engineering
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• v.13 no.2
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• pp.139-143
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• 2015

A push-push voltage controlled dielectric resonator oscillator (VCDRO) with a modified frequency tuning structure using broadside couplers is investigated. The push-push VCDRO designed at 16 GHz is manufactured using a low temperature co-fired ceramic (LTCC) technology to reduce the circuit size. The frequency tuning structure using a broadside coupler is embedded in a layer of the A6 substrate by using the LTCC process. Experimental results show that the fundamental and third harmonics are suppressed above 15 dBc and 30 dBc, respectively, and the phase noise of push-push VCDRO is -97.5 dBc/Hz at an offset frequency of 100 kHz from the carrier. The proposed frequency tuning structure has a tuning range of 4.46 MHz over a control voltage of 1-11 V. This push-push VCDRO has a miniature size of 15 mm×15 mm. The proposed design and fabrication techniques for a push-push oscillator seem to be applicable in many space and commercial VCDRO products.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.717-718
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• 2013

The output frequency of VCO(Voltage-Controlled Oscillator) with input frequency is changed if CMOS channel length and width are changed. In this paper, the electrical characteristics of VCO circuit is used as a part of FLL circuit are simulated with CMOS channel width. And the method is introduced to improve the reliability characteristics of VCO with channel width variation.