• Journal of Power Electronics
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• 제16권3호
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• pp.925-935
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• 2016

This paper proposes a new interleaved double-input three-level Boost (DITLB) converter, which is composed of two boost converters indirectly in series. Thus, a high voltage gain, together with a low component stress and a small input current ripple due to the interleaved control scheme, is achieved. The operating principle of the DITLB converter under the individual supplying power (ISP) and simultaneous supplying power (SSP) mode is analyzed. In addition, closed-loop control strategies composed of a voltage-current loop and a voltage-balance loop, have been researched to make the converter operate steadily and to alleviate the neutral-point imbalance issue. Experimental results verify correctness and feasibility of the proposed topology and control strategies.

• Journal of Power Electronics
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• 제12권5호
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• pp.739-747
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• 2012

This paper applies carrier phase shifted pulse-width modulation (CPS-PWM) to transformerless modular multilevel converters (MMC) to improve the output spectrum. Because the MMC topology is characterized by the double-star connection of six legs consisting of cascaded modular chopper cells with floating capacitors, the balance control of the DC-link capacitor voltage is essential for safe operation. This paper presents a leg-balancing control strategy to achieve DC-link voltage balance under all operating conditions. This strategy based on circulating current decoupling control focused on DC-link balancing between the upper and lower legs in each phase pair by considering the six legs as three independent phase-pairs. Experiments are implemented on a 100-V 3-kVA downscaled prototype. The experimental results show that the proposed leg-balancing control is both effective and practical.

• Journal of Power Electronics
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• 제14권4호
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• pp.661-670
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• 2014

A new DC/DC converter with zero voltage switching is proposed for applications with high input voltage and high load current. The proposed converter has two circuit modules that share load current and power rating. Interleaved pulse-width modulation (PWM) is adopted to generate switch control signals. Thus, ripple currents are reduced at the input and output sides. For high-voltage applications, each circuit module includes two half-bridge legs that are connected in series to reduce switch voltage rating to $V_{in}/2$. These legs are controlled with the use of asymmetric PWM. To reduce the current rating of rectifier diodes and share load current for high-load-current applications, two center-tapped rectifiers are adopted in each circuit module. The primary windings of two transformers are connected in series at the high voltage side to balance output inductor currents. Two series capacitors are adopted at the AC terminals of the two half-bridge legs to balance the two input capacitor voltages. The resonant behavior of the inductance and capacitance at the transition interval enable MOSFETs to be switched on under zero voltage switching. The circuit configuration, system characteristics, and design are discussed in detail. Experiments based on a laboratory prototype are conducted to verify the effectiveness of the proposed converter.

• Journal of Power Electronics
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• 제19권1호
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• pp.68-78
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• 2019

The emergence of high voltage conversion applications has resulted in a trend of using semiconductor device series associations. Series associations allow for operation at blocking voltages, which are higher than the nominal voltage for each of the semiconductor devices. The main challenge with these topologies is finding a way to guarantee the voltage balance between devices in both blocking and switching transients. Most of the methods that have been proposed to mitigate static and dynamic voltage unbalances result in increased losses within the device. This paper introduces a new series stack topology, where the voltage unbalances are reduced. This in turn, mitigates the switching losses. The proposed topology consists of a circuit that ensures the soft switching of each device, and one auxiliary circuit that allows for switching energy recovery. The principle for the topology operation is presented and experimental tests are performed for two modules. The topology performs excellently for switching transients on each of the devices. The voltage static unbalances were limited to 10%, while the activation/deactivation delay introduced by the lower module IGBT driver takes place in the dynamic unbalances. Thus, the switching losses are reduced by 40%, when compared to hard switching configurations.

• Journal of Power Electronics
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• 제18권5호
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• pp.1315-1324
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• 2018

A novel three-phase four-wire inverter topology is presented in this paper. This topology is equipped with a special capacitor balance grid without magnetic saturation. In response to unbalanced load and unequal split DC-link capacitors problems, a qusi-full-bridge DC/DC topology is applied in the balance grid. By using a high-frequency transformer, the energy transfer within the two split dc-link capacitors is realized. The novel topology makes the voltage across two split dc-link capacitors balanced so that the neutral point voltage ripple is inhibited. Under the condition of a stable neutral point voltage, the three-phase four-wire inverter can be equivalent to three independent single phase inverters. As a result, the three-phase inverter can produce symmetrical voltage waves with an unbalanced load. To avoid forward transformer magnetic saturation, the voltages of the primary and secondary windings are controlled to reverse once during each switching period. Furthermore, an improved mode chosen operating principle for this novel topology is designed and analyzed in detail. The simulated results verified the feasibility of this topology and an experimental inverter has been built to test the power quality produced by this topology. Finally, simulation results verify that the novel topology can effectively improve the inhibition of an inverter with a three-phase unbalanced load while decreasing the value of the split capacitor.

• 전력전자학회논문지
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• 제7권1호
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• pp.65-73
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• 2002

본 논문에서는 플라잉 커패시터 멀티-레벨 인버터의 가장 큰 문제점인 커패시터 전압 불균형을 캐리어 비교방식을 토대로 한 펄스 폭 변조 방식(PWM)을 이용하여 제어하는 새로운 PWM방법을 제안한다. 제안된 방법은 멜티-레벨 인버터로 확장이 용이한 캐리어 비교 방식의 PWM방법으로서 플라잉 커패시터 인버터에서 소자의 스위칭시각 커패시터의 충·방전으로 인해 발생되는 전압불균형에 대해 상전압 리던던시와 선간전압 리던던시를 이용하여 커패시터 전압의 변화량을 일정주기에 대해 평균적으로 영으로 제어하게 된다. 또한 이 방법은 상전압 리던던시를 고르게 이용하여 소자의 스위치 손실과 도통 손실을 같게 하는 장점을 지닌다. 본문에서 플라잉 커패시터 인버터에 서 발생하는 커패시터 전압 불균형에 대해 분석하고 이 인버터에 적합한 캐리어 비교방식의 PWM방법을 설명한다.

• 전력전자학회논문지
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• 제4권1호
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• pp.99-104
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• 1999

최근 산업이 대규모화함에 따라 고압 전력 변환 장치의 필요성이 증가하고 있고, 이에 따라 전력용 반도체 소자의 직렬 구동이 많이 이용되고 있다. 소자의 직렬 구동은 소자간에 적절한 전압 분배가 이루어져 개별 소자에 정격이상의 과전압이 인가되는 것을 방지하는 것이 큰 관건이다. 또한 고전압 회로에서는 부유 인덕턴스에 의한 소자의 과전압도 방지하여야 한다. 본 논문에서는 직렬 연결된 IGBT의 턴-오프 과도상태시 컬렉터 전압 기울기 조절로 안정된 전압 분배와 과전압을 방지하는 새로운 게이트 구동기법을 제안한다. 제안하는 게이트 구동기법은 컬렉터 전압을 검출하여 능동적으로 게이트 신호를 제어함으로써 과전압을 제한한다. 새로운 IGBT 게이트 구동회로를 제작하고 직렬 연결된 IGBT 회로에 적용하여 게이트 구동기법의 타당성을 검증하였다.

• Journal of Power Electronics
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• 제9권2호
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• pp.133-145
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• 2009

In this paper a modular high performance MV-to-LV rectifier based on a cascaded H-bridge rectifier is presented. The proposed rectifier can directly connect to the medium voltage levels and provide a low-voltage and highly-stable DC interface with the consumer applications. The input stage eliminates the necessity for heavy and bulky step-down transformers. It corrects the input power factor and maintains the voltage balance among the individual DC buses. The second stage includes the high frequency parallel-output DC/DC converters which prepares the galvanic isolation, regulates the output voltage, and attenuates the low frequency voltage ripple ($2f_{line}$) generated by the first stage. The parallel-output converters can work in interleaving mode and the active load-current sharing technique is utilized to balance the load power among them. The detailed analysis for modeling and control of the proposed structure is presented. The validity and performance of the proposed topology is verified by simulation and experimental results.

• 전기학회논문지
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• 제58권2호
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• pp.301-307
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• 2009

In the paralleled converter module with peak current mode control, current imbalance appears when the voltage controllers with integral control of converter module are not exactly identical. In this paper, the voltage controller is designed to equal the current command of each converter module using the current command bus. The current balance controller is also proposed to balance the average currents of converter modules with imbalaced inductance. It is designed to have good transient response. Proposed method is implemented with the paralleled 2-module and 4-module boost converters with imbalanced inductance. Experimental results verify the performance of current share during both steady and transient states of converter.

• Journal of Power Electronics
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• 제19권2호
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• pp.487-496
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• 2019

For a solid-state transformer (SST), some factors, such as signal delay, switching loss and differences in the system parameters, lead to unbalanced DC-link voltages among the cascaded H-bridges (CHB). With a control method implemented in the ${\alpha}{\beta}$ frame, the DC-link voltages are balanced, and the reactive power is equally distributed among all of the H-bridges. Based on the ${\alpha}{\beta}$ frame control, the system can achieve independent active current and reactive current control. In addition, the control method of the high-voltage stage is easy to implement without decoupling or a phase-locked loop. Furthermore, the method can eliminate additional current delays during transients and get the dynamic response rapidly without an imaginary current component. In order to carry out the controller design, the vector refactoring relations that are used to balance DC-link voltages are derived. Different strategies are discussed and simulated under the unbalanced load condition. Finally, a three-cell CHB rectifier is constructed to conduct further research, and the steady and transient experimental results verify the effectiveness and correctness of the proposed method.