• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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• v.2B no.3
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• pp.81-89
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• 2002

The sensorless AC motor drive is a popular topic of study due to the cost and reliability of speed and position sensors. Most sensorless algorithms are based on the mathematical modeling of motors including electrical variables such as phase current and voltage. Therefore, the accuracy of such variables largely affects the performance of the sensorless AC motor drive. However, the output voltage of the SVPWM-VSI, which is widely used in sensorless AC motor drives, has considerable errors. In particular, the SVPWM-VSI is error-prone in the low speed range because the constant DC link voltage causes poor resolution in a low output voltage command and the output voltage is distorted due to dead time and voltage drop. This paper investigates a novel high-performance strategy for overcoming these problems in a sensorless ac motor drive. In this paper, a variation of the DC link voltage and a direct compensation for dead time and voltage drop are proposed. The variable DC link voltage leads to an improved resolution of the inverter output voltage, especially in the motor's low speed range. The direct compensation for dead time and voltage drop directly calculates the duration of the switching voltage vector without the modification of the reference voltage and needs no additional circuits. In addition, the proposed strategy reduces a current ripple, which deteriorates the accuracy of a monitored current and causes torque ripple and additional loss. Simulation and experimentation have been performed to verify the proposed strategy.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.954-955
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• 2008

In this paper, the voltage harmonics are investigated in terms of the voltage sag versus the time constants of electric machinery under the source voltage variation condition. The electric machinery and compensation equipment are established on the proposed design scheme based on voltage quality effect assessment technology. It have been analyzed how the variation of harmonic order, the output current, the DC-Link voltage and the induction motor speed is carried out under the voltage sag and switching frequency variation.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.4
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• pp.351-357
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• 1999

This paper proposes the coordinated control of SVC and UTLC at the distribution substation to get larger operating margin of SVC for the voltage stability control by reactive power compensation. In the conventional method, ULTC doesn't respond to the variation of source voltage, so SVC has the entire responsibility for it. It could cause the lack of operating margin of SVC in some condition. It, however, is important to secure an operating margin for the dynamic stability control in emergancy. This paper proposes the coordinated control method that SVC controls the supply voltage and ULTC respond to the SVC compensation valve based on the relation between SVC compensation and ULTC tap position. The numerical simulation verifies that the proposed system could increase the operating margin of SVC compared with the conventional system.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.15 no.3
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• pp.205-210
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• 2022

A novel OLED pixel circuit is proposed in this paper that uses only n-type thin-film transistors(TFTs) to improve the luminance non-uniformity of the AMOLED display caused by the threshold voltage variation of an OLED driving TFT. The proposed OLED pixel circuit is composed of 6 n-channel TFTs and 2 capacitors. The operation of the proposed OLED pixel circuit consists of the capacitor initializing period, threshold voltage sensing period of an OLED·driving TFT, image data voltage writing period, and OLED·emitting period. As a result of SmartSpice simulation, when the threshold voltage of·OLED·driving TFT varies from 1.2 V to 1.8 V, the proposed OLED pixel circuit has a maximum current error of 5.18 % at IOLED = 1 nA. And, when the OLED cathode voltage rises by 0.1 V, the proposed OLED pixel circuit has very little change in the OLED current compared to the conventional OLED pixel circuit. Therefore, the proposed pixel circuit exhibits superior compensation characteristics for the threshold voltage variation of an OLED driving TFT and the rise of the OLED cathode voltage compared to the conventional OLED pixel circuit.

• Journal of Korea Multimedia Society
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• v.21 no.9
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• pp.1068-1075
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• 2018

We propose a method for driving loudspeakers from class D audio power amplifiers in current mode, instead of in conventional voltage mode, which was impossible with the feedback circuitry. Unlike analog audio amplifiers, Class D audio power amplifiers have signal delay between the input and output signals, which makes it difficult to apply the feedback circuitry for current-mode driving. The idea of the pre-distortion scheme used for the compensation of the non-linearity of RF power amplifiers is adapted to remedy the impedance variation effect of the loudspeakers for current driving. The method uses the speaker model for the pre-distorter to compensate for the speaker impedance variation with frequency. The simulation and test results confirms the validity of the proposed method.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.55 no.12
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• pp.514-521
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• 2006

The existing ULTC operation control strategy based on the measured data deteriorates the voltage compensation capability making the efficient corresponding to the load variation difficult by following the fixed load center point voltage. Accordingly, this paper proposes a new on-line fuzzy ULTC controller based on the designed multiple load center points which can improve the voltage compensation capability of ULTC and minimize voltage deviation by moving in real-time the load center point according to the load variation to an adequate position among the multiple load center points designed using the clustering technique. The Max-Min distance technique is adopted as the clustering technique for the decision of multiple load points from measured MTr load current and PTr voltage, and the minimum distance classifier is adopted for the decision of fuzzy output membership function. To verify the effectiveness of the proposed strategy, Visual C++ MFC-based simulation environments is developed. Finally, the superiority the proposed strategy is proved by comparing the fuzzy ULTC operation control results based on multiple load center points with the existing ULTC operation control results based on fixed load center point using the data for three day.

• Proceedings of the KIEE Conference
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• 1998.11b
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• pp.403-406
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• 1998

There are two cases of error occurrence of STT(Smart Temperature Transmitter). One is that because of unstable reference voltage, data from A/D converter is not reliable. The other is that because of change of room temperature, this change affects conversion of A/D converter. In this paper, we show algorithms be adapted to STT for reliable conversion of A/D converter through a experiment and compensation for temperature change. In a experiment, we collect data from reference voltage and ground then calculate nominal value of these at constant temperature during A/D converter initialization or at any conversion time. Algorithm for compensation for unstable reference voltage calculates a correction factor and adapts it to compensation for malfunction of A/D converter. Algorithm for compensation for variation of room temperature is come from linearization of thermistor but is adapted to zener diode, not thermistor, therefor we have less effort for compensation for temperature and have a idea that it can be adapted to A/D converter system.

• KIEE International Transactions on Power Engineering
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• v.5A no.3
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• pp.252-259
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• 2005

Various problems such as increase of power loss and voltage instability may often occur in the case of low load power factor. The demand of reactive power increases continuously with the growth of active power and restructuring of electric power companies makes the comprehensive management of reactive power a troublesome problem, so that the systematic control of load power factor is required. In this paper, the load power factor sensitivity of generation cost is derived and it is used for effectively determining the locations of reactive power compensation devices and for enhancing the load power factor appropriately. In addition, voltage variation penalty cost is introduced and integrated costs including voltage variation penalty cost are used for determining the value of load power factor from the point of view of economic investment and voltage regulation. It is shown through application to a large-scale power system that the load power factor can be enhanced effectively using the load power factor sensitivity and the integrated cost.

• Journal of the Korean Society for Precision Engineering
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• v.29 no.11
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• pp.1174-1177
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• 2012

In voltage measurement by using voltage divider with series resistors, error is generated caused by the variation of resistance. In order to reduce these errors, the hardware cost tends to increase in the previous works. In the proposed method, three resistors are used for the voltage divider of which the organization is adjusted by using switches. Three voltages are measured and the ratio of resistance is calculated based on the measured voltages. Since the resistance ratio is calculated by measuring voltages and additional hardware cost is minimal, the voltage can be measured with high accuracy and low cost. Experimental results show that the mean absolute error is 12.1 mV when the input voltage ranges from 5 V to 50 V.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.4
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• pp.241-246
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• 2007

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32nm predictive CMOS technology and uses a 0.9 V power supply voltage. The simulation results show that the proposed PLL achieves 88% jitter reduction at 440 MHz output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of 40 $M{\sim}725$ MHz with a multiplication range of 1-1023, and the RMS and peak-to-peak jitter are 5psec and 42.7 psec, respectively.