• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.3
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• pp.289-295
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• 2014

In this paper a wideband active balun using advanced phase correction architecture is proposed. The proposed active balun is constructed with each different architecture of active balun combined with the cascode architecture to improve phase correction performance compared with conventional phase correction techniques. Operating over 0.6~2.0 GHz band, the proposed balun shows $10^{\circ}$ of phase error and 2 dB of gain error with 7 mW power consumption from 1.8 V supply voltage.

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.163-167
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• 2000

This paper presents the digital control of single-phase power factor correction(PFC) converter which has the variable gain according to the condition of inner control loop error. Generally the gain of inner current control loop in single-stage PFC converter has a constant magnitude. This has a bad influence on the power factor because current loop doesn't operate smoothly in the condition that input voltage is low In particular a digital controller has more time delay than an analog controller and degrades This drops the phase margin of the total digital PFC system,. It causes the problem that the gain of current control loop isn't increased enough. In addition the oscillation happens in the peak value of the input voltage open loop PFC system gain changes according to ac input voltage. These aspects make the design of the digital PFC controller difficult The digital PFC controller presented in this paper has a variable gain of current control loop according to input voltage. The 1kW converter was used to verify the efficiency of the digital PFC controller.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2002.11a
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• pp.349-354
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• 2002

A size of low-voltage conductor cables is determined by the voltage drop of a system, the cable impedance and the cable ampacity based on temperature correction factor in accordance with the condition of cable installation. Therefore, the proper temperature correction factor according to the condition of cable installation should be applied to determining the cable ampacity and also the skin effect and proximity effect, along with the kind and size of conductor and the condition of cable installation, should be properly considered to analyze the proper value of resistance and the reactance of the conductors. This paper addresses the systematic design flow for determining the size of low voltage level conductor cables in calculating the temperature character where error should be minimized in comparison with the general formula and which can be applied in design work for determining the size of conductor cables.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.901-904
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• 2005

A novel active matrix organic light diodes (AMOLEDs) voltage-programming pixel structure with current-correction method is proposed for largesize and high-resolution poly-Si AMOLED panel applications. The HSPICE simulation results shows that the maximum error of emission current in proposed pixel is 1.536%, 2.45%, and 2.97% with the ${\pm}12.5%$ mobility variation and ${\pm}0.3V$ threshold voltage variation for 30-, 40-, and 50-inch HDTV panels, respectively.

• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.4
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• pp.1-7
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• 1985

In this paper, a more improved threshold voltage model dependent on drain voltage and substrate bias for short - channel enhancement - mode IGFET is presented. Especially, compared with the several recently published models, the error is sufficiently reduced with the precise analysis on the correction factor for short-channel effect and the calculated values using this model are also agreed well with the experimental data about 1$\mu$m - channel length device.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.37 no.2
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• pp.175-181
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• 2024

In electrical power substations, bulky iron-core potential transformers (PTs) are installed in a tank of gas-insulated switchgear (GIS) to measure system voltages. This paper proposed a low-power voltage transformer (LPVT) that can replace the conventional iron-core PTs in response to the demand for the digitalization of substations. The prototype LPVT consists of a capacitive voltage divider (CVD) which is embedded in a spacer and an impedance matching circuit using passive components. The CVD was fabricated with a flexible PCB to acquire enough insulation performance and withstand vibration and shock during operation. The performance of the LPVT was evaluated at 80%, 100%, and 120% of the rated voltage (38.1 kV) according to IEC 61869-11. An accuracy correction algorithm based on LabVIEW was applied to correct the voltage ratio and phase error. The corrected voltage ratio and phase error were +0.134% and +0.079 min., respectively, which satisfies the accuracy CL 0.2. In addition, the voltage ratio of LPVT was analyzed in ranges of -40~+40℃, and a temperature correction coefficient was applied to maintain the accuracy CL 0.2. By applying the LPVT proposed in this paper to the same rating GIS, it can be reduced the length per GIS bay by 11%, and the amount of SF6 by 5~7%.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.39 no.2
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• pp.133-141
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• 1990

In the operation of an electric power system, the voltage security of the system has acquired more significant importance after the occurrence of large system black-outs caused by voltage collapse several times. This paper describes a fast contingency screening method concerning voltage security. The method defines a voltage-sensitive buses where significant voltage changes would occur as a result of the contingency to reduce the number of bus voltages to be solved for continngency screening. This method is based on the observation that it is not necessary to solve the entire network in most contingency cases because boltage changes actually occur around the contingency. The P-Q decoupled linearized model and the fast error correction method are also adopted in the method to define voltage-sensitive buses and to calculate voltage magnitude on the selected voltage-sensitive buses fastly and reliably. The method suggested in this papaer has been tested in IEEE 30-bus model system and KEPCO 130-bus actual system and its effectiveness for practical use has also been confirmed.

• Journal of Institute of Control, Robotics and Systems
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• v.3 no.4
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• pp.357-362
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• 1997

This paper suggests an automatic calibration technique for piezoelectric low pressure transducer measuring a pressure blow 500psi. The present calibration system embedded with error correction algorithm generates it's best you don't cut parts of wards like so dynamic pressure and compensates offset voltage and pressure error. It is shown via experimental results that the instrumentation accuracy has been improved and mean time between calibrations has been shortened.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.48-55
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• 2009

This paper presents a high-speed Forward Error Correction (FEC) architecture based on three-parallel Reed-Solomon (RS) decoder for next-generation 100-Gb/s optical communication systems. A high-speed three-parallel RS(255,239) decoder has been designed and the derived structure can also be applied to implement the 100-Gb/s RS-FEC architecture. The proposed 100-Gb/s RS-FEC has been implemented with 0.13-${\mu}m$ CMOS standard cell technology in a supply voltage of 1.2V. The implementation results show that 16-Ch. RS-FEC architecture can operate at a clock frequency of 300MHz and has a throughput of 115-Gb/s for 0.13-${\mu}m$ CMOS technology. As a result, the proposed three-parallel RS-FEC architecture has a much higher data processing rate and low hardware complexity compared with the conventional two-parallel, three-parallel and serial RS-FEC architectures.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.54 no.11
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• pp.493-497
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• 2005

This paper dealt with the influence of harmonic voltages on arrester diagnostics and its compensation method by using a designed Pspice arrester model. A pure sinusoidal voltage and its 3$^{rd}$ harmonic voltage were applied to the model, and the leakage current components were analyzed. The simulation results have shown that the peak value of resistive leakage current depends not only on the phase of the 3$^{rd}$ harmonic voltage but also on the magnitude of it. In this paper, an approximated 5$^{th}$ order polynomial formula by the Least-Square-Technique was derived, and correction factors which compensate the error caused by the 3$^{rd}$ harmonic voltage were calculated.